Method to fill the gap between coupled wafers

Details Method to fill the gap between coupled wafers Method to fill the gap between coupled wafers

2006-08-08

2006-08-08

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S792000, C438S906000

Reexamination Certificate

active

07087538

ABSTRACT:
A three-dimensional integrated circuit formed by applying a material to fill a gap between coupled wafers and slicing the coupled wafers into dice. A method for filling a gap between coupled wafers. Various embodiments include at least one of spinning a coupled wafer pair, drilling a hole into one of the coupled wafers, and using a vacuum to aid in the dispersion of the material.

REFERENCES:
patent: 3648131 (1972-03-01), Stuby
patent: 3705332 (1972-12-01), Parks
patent: 4607779 (1986-08-01), Burns
patent: 4689113 (1987-08-01), Balasubramanyam et al.
patent: 4897708 (1990-01-01), Clements
patent: 4954875 (1990-09-01), Clements
patent: 4998665 (1991-03-01), Hayashi
patent: 5045914 (1991-09-01), Casto et al.
patent: 5229647 (1993-07-01), Gnadinger
patent: 5241450 (1993-08-01), Bernhardt et al.
patent: 5283107 (1994-02-01), Bayer et al.
patent: 5366906 (1994-11-01), Wojnarowski et al.
patent: 5401672 (1995-03-01), Kurtz et al.
patent: 5404044 (1995-04-01), Booth et al.
patent: 5419806 (1995-05-01), Huebner
patent: 5455445 (1995-10-01), Kurtz et al.
patent: 5473197 (1995-12-01), Idaka et al.
patent: 5510655 (1996-04-01), Tanielian
patent: 5545281 (1996-08-01), Matsui et al.
patent: 5608265 (1997-03-01), Kitano et al.
patent: 5627106 (1997-05-01), Hsu
patent: 5640049 (1997-06-01), Rostoker et al.
patent: 5656554 (1997-08-01), Desai et al.
patent: 5699611 (1997-12-01), Kurogi et al.
patent: 5717247 (1998-02-01), Koh et al.
patent: 5751556 (1998-05-01), Butler et al.
patent: 5773986 (1998-06-01), Thompson et al.
patent: 5825080 (1998-10-01), Imaoka et al.
patent: 5880010 (1999-03-01), Davidson
patent: 5886535 (1999-03-01), Budnaitis
patent: 5901050 (1999-05-01), Imai
patent: 5998808 (1999-12-01), Matsushita
patent: 6100181 (2000-08-01), You et al.
patent: 6165864 (2000-12-01), Shen et al.
patent: 6238951 (2001-05-01), Caillat
patent: 6255726 (2001-07-01), Vindasius et al.
patent: 6297072 (2001-10-01), Tilmans et al.
patent: 6340608 (2002-01-01), Chooi et al.
patent: 6355501 (2002-03-01), Fung et al.
patent: 6355976 (2002-03-01), Faris
patent: 6373130 (2002-04-01), Salaville
patent: 6391669 (2002-05-01), Fasano et al.
patent: 6459148 (2002-10-01), Chun-Jen et al.
patent: 6461890 (2002-10-01), Shibata
patent: 6468098 (2002-10-01), Eldridge
patent: 6495924 (2002-12-01), Kodama et al.
patent: 6504253 (2003-01-01), Mastromatteo et al.
patent: 6559042 (2003-05-01), Barth et al.
patent: 6583512 (2003-06-01), Nakaoka et al.
patent: 6593645 (2003-07-01), Shih et al.
patent: 6594025 (2003-07-01), Forouhi et al.
patent: 6608371 (2003-08-01), Kurashima et al.
patent: 6643920 (2003-11-01), Hori
patent: 6653725 (2003-11-01), Ahn et al.
patent: 6661085 (2003-12-01), Kellar et al.
patent: 6724084 (2004-04-01), Hikita
patent: 6762076 (2004-07-01), Kim et al.
patent: 6882045 (2005-04-01), Massingill et al.
patent: 2001/0038148 (2001-11-01), Mastromatteo et al.
patent: 2002/0017710 (2002-02-01), Kurashima et al.
patent: 2002/0024628 (2002-02-01), Walker et al.
patent: 2002/0163072 (2002-11-01), Gupta et al.
patent: 2002/0195673 (2002-12-01), Chou et al.
patent: 2003/0079836 (2003-05-01), Lin et al.
patent: 2003/0148596 (2003-08-01), Kellar et al.
patent: 2003/0157782 (2003-08-01), Kellar et al.
patent: 2004/0014308 (2004-01-01), Kellar et al.
patent: 2004/0142540 (2004-07-01), Kellar et al.
patent: 0 293 459 (1987-12-01), None
patent: WO 88/04829 (1988-06-01), None
Vendier et al.,Ultra Thin Electronics for Space Applications, 2001 Electronic Components and Technology Conference, Copyright 2001, IEEE, 5 pages.
Fan et al.,Cooper Wafer Bonding, Electrochemical and Solid-State Letters, Copyright the Electrochemical Society, Inc., 1999, 3 pages.
McDonald et al.,Face to Face Wafer Bonding for 3D Chipstack Fabrication to Shorten Wire Lengths, Jun. 27-29, 2000 VMIC Conference, pp. 90-94.
Ramm et al., InterChip Technology for Verical System Integration, Fraunhofer Institute for Reliability and Microintegration, Munich Germany, Infineon Technologies AG, Munich Germany, Copyright 2001 IEEE, pp. 160-162.

Affiliated with

Also associated with

Rating

Method to fill the gap between coupled wafers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to fill the gap between coupled wafers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to fill the gap between coupled wafers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3649149