Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Reexamination Certificate
1998-08-11
2003-12-30
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Signal level or switching threshold stabilization
C326S083000, C326S086000
Reexamination Certificate
active
06670822
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to circuitry for transmitting electrical signals from one location to another. In particular, the present invention relates to output drivers designed to provide timely transmission of such signals at required potentials and with sufficient current for communications between coupled devices. Still more particularly, the present invention relates to circuitry for regulating the transition of logic signals between “high” and “low” levels, including those associated with Complementary Metal-Oxide-Silicon (CMOS) transistor-based output drivers.
2. Description of the Prior Art
Output drivers are used to transfer electrical signals of desired amplitude and strength. Signal transfers occur by way of buses—interfaces that couple active devices that are either on the same semiconductor-based chip or on different chips. The devices may be located proximate to one another, or they may be some distance from one another. One example of a proximate device interface requiring one or more bus connections is the coupling of one printed circuit board to another within a computing system, such as through a backplane bus. An example of a remote device interface requiring one or more bus connections is the coupling of one computing system to another, such as through a telephone transmission line that is, effectively, a voice/data bus.
A continuing goal in all computing and communication systems is to be able to transfer electrical signals accurately and as quickly as possible. In order to achieve that goal, it is important that those signals are transmitted at relatively uniform rates, amplitudes, and strengths. This is more likely to occur within a single computing system, less so when interfacing of a plurality of non-uniform computing systems is involved. Protocols have been developed to provide for transmission rate, amplitude, and strength uniformity so as to develop compatibility between systems and between sub-systems.
Since different active devices operate at different rates, e.g., printers versus memory devices, and have different load drains as a function of internal operations, each device requires one or more output drivers to meet transmission uniformity requirements. Output drivers are needed to increase signal gain prior to output to a bus, they are required to slow or increase the transmission rate of a signal to be delivered, or a combination of the two. It is to be understood that these “output” drivers may also operate to receive transmissions from the bus for delivery back to the active device for interpretation and action, if any. Given this dual operation capability, these unifying drivers are generally identified as transceivers.
It is well known that in digital systems the signals moving between devices are categorized as either logic level high (or “1” or “ON”) and logic level low (or “0” or “OFF”). The particular signal potential that defines whether a logic high or a logic low is being transmitted is dependent upon the semiconductor components that form the circuitry associated with that transmission. The most common circuit configurations used to produce digital signals include, among others, CMOS, Transistor-Transistor:Logic (TTL), and Emitter-Coupled Logic (ECL)—positive ECL (PECL) in particular. Each of these logic configurations operates differently as a function of the “swing” between what constitutes a logic high signal and what constitutes a logic low signal.
For CMOS logic, which is based primarily on the use of MOS transistors, a logic low signal is generally developed in the range of 0.6 volts (V) above a low-potential power rail GND, which may be at 0.0V. A logic high signal is generally developed in the range of Vcc to Vcc-0.6V, where Vcc may vary between 4.5V and 5.5V for a nominal 5-volt supply, or between 3.0V and 3.6V for a nominal 3.3-volt supply. For a 5-volt supply then, the differential swing between low and high must be at least 3.9 volts in order to ensure that a desired shift between a logic low and a logic high will occur. TTL and ECL logic configurations, on the other hand, are based primarily on the use of bipolar transistors. The differential swing for a shift between a logic low and a logic high is significantly less than it is for CMOS operation-it may as low as 1.0 volt. For PECL systems, for example, the swings are even closer. In PECL circuitry, which is Vcc dependent, a logic high is equivalent to a potential of about Vcc-0.9V, and a logic low is equivalent to a potential of about Vcc-1.7V. Thus, in mating CMOS and non-CMOS transmissions, it can be seen that variations in potential swings will not automatically ensure the triggering of a desired swing from one logic level to another. Furthermore, minor potential swings in CMOS signals may not effect any logic level change therein; however, they may be significant enough to cause an unexpected change in a TTL or an ECL logic value when transmitted to a TTL- or an ECL-based system.
Clearly, unexpected changes in logic values are not desirable. They can cause significant operational errors. Therefore, it is important to provide a transceiver driver that will not generate excessive signal potential swings—other than those specifically desired to achieve a logic level shift. This problem is more likely to occur as transmission rates are increased. Increasing transmission rates enables the transfer of more data in a shorter time period and so is desirable in many respects. However, the gain in increased transmission rate is often undermined by an increase in signal noise. That is, a rapid change in signal level creates an oscillation about the steady state value corresponding to the sudden switching on or off of a transistor. The extent of the oscillation is dependent upon the particular transistor system used as well as the loading on the backplane bus.
As transistors become increasingly smaller in order to achieve the faster transmission rates of interest, the corresponding differential swings associated with their logic outputs are reduced. When the wider-swing CMOS logic systems interface with smaller-swing bipolar-transistor-based logic systems the noise associated with CMOS operation may generate enough of a swing to cause an undesired transistor switching. The signal bounce that occurs with the rapid switching often creates reflections in transmission media, such as telephone transmission lines where reflections will cause signal errors. It is therefore important to enable “gentle” switching of driver transistors so that signal noise is reduced when logic levels are changed.
One means for achieving some success in smoothing signal transitions in a transceiver driver has been described in U.S. Pat. No. 5,557,223 issued to Kuo. As illustrated in
FIG. 1
, a CMOS-based signal output driver
10
includes means intended to induce gentle switching of signal transmission. The Kuo driver includes first inverter stage
20
, formed of first inverter I
1
for receiving an incoming signal INPUT that is to be transmitted, and second inverter I
2
. Those components, along with third inverter stage
13
, current mirroring transistors M
199
and M
197
, and output transistor M
202
are all relatively standard components of an output driver for delivering output signal OUTPUT. Transistors M
197
and M
199
are always on, as can be seen from their coupling and the use of temperature-compensation gate drivers TCD
1
and TCD
2
, respectively. The Kuo circuit further includes discharge circuit
30
that is coupled to the gate of transistor M
202
for the purpose of slowing the switching of that output transistor so that signal bounce and reverberation may be minimized. Discharge circuit
30
includes first discharge transistor M
440
, second discharge transistor M
441
, and inverter I
4
.
The Kuo circuit
10
is designed to provide a built-in delay in the discharge of transistor M
202
. An input signal at node INPUT that produces a logic high at the gate of transistor M
202
also produces a logic high at the gate of transis
Cesari and McKenna LLP
Fairchild Semiconductor Corporation
Le Don Phu
Paul, Esq. Edwin H.
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