Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-08-14
2007-08-14
Vu, Hung (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S396000, C438S648000
Reexamination Certificate
active
09962786
ABSTRACT:
An improvement in the method of fabricating on chip decoupling capacitors which help prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. The inclusion of a hybrid metal/metal nitride top electrode/barrier provides for a low cost and higher performance option to strapping decoupling capacitors.
REFERENCES:
patent: 5976928 (1999-11-01), Kirlin et al.
patent: 6027980 (2000-02-01), Gardner
patent: 6180482 (2001-01-01), Kang
patent: 6278147 (2001-08-01), Dalton et al.
patent: 6297527 (2001-10-01), Agarwal et al.
patent: 6339258 (2002-01-01), Cooney, III et al.
Syd R. Wilson, Clarence J. Tracy, and John L. Freeman, Jr., “Handbook of Multilevel Metallization for Integrated Circuits,” Noyes Publ., Westwood, New Jersey, (1993), p. 42.
Hiroyuki Shimada, Ichiro Ohshima, Shin-Ichi Nakao, Munekatsu Nakagawa, Kei Kanemoto, Masaki Hirayama, Shigetoshi Sugawa, and Tadahiro Ohmi, “Low Resistivity bcc-Ta/TaNx Metal Gate MNSFETs Having Plane Gate Structure Featuring Fully Low-Temperature Processing Below 450 C,” Digest of Technical Papers- Symposium on VLSI Technology, (2001), pp. 67-68.
S.C. Sun, M.H. Tsai, C.E. Tsai, and H.T. Chiu, “Properties of Metalorganic Chemical Vapor Deposited Tantalum Nitride Thin Films,” Proc. 4thInt'l Conf. on Solid State and Integrated Circuit Tech. (1995), pp. 547-549.
Hiroyuki Shimada, Ishiro Oshima, Takeo Ushiki, Shigetoshi Sugawa and Tadahiro, “Tantalum Nitride Metal Gate FD-SOI CMOS FETs Using Low Resistivity Self-Grown bcc-Tantalum Layer,” IEEE Trans. on Electron Devices, vol. 48 (Aug. 2001) pp. 1619-1627.
S.M. Sze, “Physics of Semiconductor Devices,” John Wiley & Sons, New York (1981), Appendix I.
S. Wolf, “Silicon Processing for the VLSI Era, vol. 4—Deep Submicron Process Technology,” Lattice Press, Sunset Beach, CA (2002) p. 720.
Block Bruce A.
List Richard Scott
Zhang Ruitao
Intel Corporation
Vu Hung
LandOfFree
Top electrode barrier for on-chip die de-coupling capacitor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Top electrode barrier for on-chip die de-coupling capacitor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Top electrode barrier for on-chip die de-coupling capacitor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3892791