Token mechanism for cache-line replacement within a cache memory

Details Token mechanism for cache-line replacement within a cache memory Token mechanism for cache-line replacement within a cache memory

1996-12-23

2000-03-21

Peikari, B. James

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711133, 711134, 711146, G06F 1212

Patent

active

060413905

ABSTRACT:
A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated. Each token register also has a bypass circuit. A bypass circuit is utilized to transfer the token from one token register to an adjacent token circuit in response to an indication from the associated allocation-indicating circuit.

REFERENCES:
patent: 5043870 (1991-08-01), Ditzel et al.
patent: 5155825 (1992-10-01), Moughanni et al.
patent: 5410697 (1995-04-01), Baird et al.
patent: 5553254 (1996-09-01), Berstis et al.
patent: 5611074 (1997-03-01), Kantz et al.

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