Tip architecture with SPE for buffer and deep source/drain...

Details Tip architecture with SPE for buffer and deep source/drain... Tip architecture with SPE for buffer and deep source/drain...

2006-05-16

2006-05-16

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S304000, C438S306000

Reexamination Certificate

active

07045433

ABSTRACT:
A method of manufacturing a semiconductor device includes forming a gate, source/drain extensions, buffer regions, and source/drain regions. The gate is formed over a semiconductor layer, and the source/drain extensions are formed within the semiconductor layer and adjacent the gate. The buffer regions are formed within first amorphous implant regions, and the source/drain regions are formed within second amorphous implant regions. The buffer regions and the source/drain regions are activated using solid-phase epitaxy whereby sidewalls of the activated buffer regions and the activated source/drain regions are substantially vertical.

REFERENCES:
patent: 6225176 (2001-05-01), Yu
patent: 6506650 (2003-01-01), Yu
patent: 6689671 (2004-02-01), Yu et al.
patent: 6893909 (2005-05-01), Wang et al.

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