Timing verifier for MOS devices and related method

Details Timing verifier for MOS devices and related method Timing verifier for MOS devices and related method

2005-04-05

2005-04-05

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06877142

ABSTRACT:
The present invention relates to a method and apparatus for determining capacitances and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

REFERENCES:
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5452225 (1995-09-01), Hammer
patent: 5548526 (1996-08-01), Misheloff
patent: 5559715 (1996-09-01), Misheloff
patent: 5748489 (1998-05-01), Beatty et al.
patent: 6473888 (2002-10-01), Nassif et al.

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