Timing skew compensation technique for parallel data channels

Details Timing skew compensation technique for parallel data channels Timing skew compensation technique for parallel data channels

2005-03-29

2005-03-29

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C375S355000

Reexamination Certificate

active

06874097

ABSTRACT:
A method and apparatus for correcting the timing skew of data signals in a parallel data transmission system, such as Small Computer System Interface (SCSI) data bus, relative to a receive clock in the data bus. The system separately corrects the receive clock duty cycle, and also features independent de-skewing of the rising and falling edges of a data waveform to improve timing accuracy of transmitted signals. The method and apparatus can be used without substantial changes to existing transmission system protocols, and can be implemented on an all-digital integrated circuit.

REFERENCES:
patent: 5467464 (1995-11-01), Oprescu et al.
patent: 5968180 (1999-10-01), Baco
patent: 6031847 (2000-02-01), Collins et al.
patent: 6553505 (2003-04-01), Brown et al.
SCSI Trade Association, “Ultra320 SCSI : New Technology—Still SCSI”, Mar. 2001.

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