Timing recovery in a packet network using a buffer

Details Timing recovery in a packet network using a buffer Timing recovery in a packet network using a buffer

2005-04-12

2005-04-12

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C710S058000, C370S235000

Reexamination Certificate

active

06880098

ABSTRACT:
A packet device is disclosed for recovering timing information from packets that were transmitted over a packet network. The packet device is comprised of a buffer and a synchronization system that includes a clock. The buffer receives packets that were transmitted based on a transmitter timing signal, and fills to a target number of packets. The buffer receives a receiver timing signal from the clock, and transfers the packets based on the receiver timing signal. The synchronization system determines a measured number of the packets in the buffer at any given time. The synchronization system compares the measured number to the target number to recover timing information. The synchronization system then adjusts the second timing signal based on the timing information.

REFERENCES:
patent: 5132964 (1992-07-01), Esaki
patent: 6504838 (2003-01-01), Kwan
patent: 6538995 (2003-03-01), Cox et al.
patent: 987894 (2000-03-01), None

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