Timing of wordline activation for DC burn-in of a DRAM with the

Details Timing of wordline activation for DC burn-in of a DRAM with the Timing of wordline activation for DC burn-in of a DRAM with the

1998-08-03

2000-05-23

Dinh, Son T.

Static information storage and retrieval

Read/write circuit

Testing

365222, G11C 700

Patent

active

060672617

ABSTRACT:
A method of testing a semiconductor circuit, the semiconductor circuit including word lines connected to a storage device, address receivers receiving addresses, an address decoder decoding the addresses and selecting ones of the word lines, a self-refresh unit refreshing the word lines during a non-test mode and a test mode device controlling the semiconductor circuit in a test mode, the method comprises supplying a test mode signal to the test mode device, activating a test mode operation of the self-refresh unit, sequentially activating the word lines using the self-refresh unit, maintaining the word lines in an active condition for a predetermined time period and deactivating the word lines.

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patent: 5495448 (1996-02-01), Sachdev
patent: 5615164 (1997-03-01), Kirihata
patent: 5661690 (1997-08-01), Roohparvar
patent: 5862094 (1999-01-01), Kawabata et al.
patent: 5956281 (1999-09-01), Nakai et al.
patent: 5991214 (1999-11-01), Merritt et al.
IBM Technical Disclosure Bulletin, vol. 30, No. 10 Mar. 1988, "Staggered Block Write In A Storage Array", p. 289.

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