Timing mode selection apparatus for handling both burst mode dat

Details Timing mode selection apparatus for handling both burst mode dat Timing mode selection apparatus for handling both burst mode dat

1998-01-12

2000-05-30

Thai, Xuan M.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Protocol

710 22, G06F 1332

Patent

active

060702109

ABSTRACT:
A timing mode selection apparatus for use in a DMA transmission system having a DMA device and an input/output device directly accessible to a memory. The timing mode selection apparatus includes a microprocessor for generating a mode selection control signal for switching a timing mode. A first buffer transfers a single mode data acknowledgment signal from the DMA device to the input/output device in response to the mode selection control signal having a first logic state. A second buffer transfers a burst mode data acknowledgment signal from the DMA device to the input/output device in response to the mode selection control signal having a second logic state. An inverter inverts the mode selection control signal output from the microprocessor. The inverted mode selection control signal is applied to a control terminal of the second buffer. In this manner, the mode selecting apparatus may freely switch the DMA transmission system between a burst mode and a single mode.

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