Timing fault diagnosis method and apparatus

Details Timing fault diagnosis method and apparatus Timing fault diagnosis method and apparatus

1998-10-30

2002-06-04

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

06401227

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention generally relates to timing fault diagnostic methods and apparatuses, and more particularly to a timing fault diagnostic method and apparatus for diagnosing a timing fault of an integrated circuit chip in which a logic circuit is formed.
As the integration density of the integrated circuit increases, required restrictions may be satisfied on a timing simulator or a static timing analyzing tool, but a timing fault may be generated on the actual integrated circuit chip.
When the timing error is generated in a flip-flop circuit, RAM or the like formed in the integrated circuit chip and an erroneous logic value is stored in a memory element, this erroneous stored value propagates to elements provided in subsequent stages, thereby causing an erroneous operation of the integrated circuit chip as a whole.
Accordingly, there are demands to realize a timing fault diagnostic method and apparatus which can easily detect an element which generates the timing fault, quickly analyze the timing fault, reduce the time required to design the integrated circuit, and reduce the cost involved in designing the integrated circuit.
Conventionally, methods of diagnosing faults of integrated circuit chips in which the logic circuit is formed include diagnosing the stuck fault or short (bridging) fault, and diagnosing the fault by directly observing a signal transmitted through wiring formed in the integrated circuit chip using an electron beam.
However, unlike the stuck fault and the short fault, the timing fault does not necessarily always occur, and the timing fault diagnosis requires consideration of the fuzziness of the timing fault generation. For this reason, although it is necessary to simultaneously specify the time and location where the timing fault is observed, the method of diagnosing the stuck fault and the short fault cannot simultaneously specify the time and location. Therefore, the method of diagnosing the stuck fault and the short fault cannot be utilized to diagnose the timing fault.
In addition, according to the conventional fault diagnostic method which uses the electron beam, it is possible to diagnose the timing fault, but it is difficult to observe a signal in a layer other than a surface layer of the integrated circuit chip. In order to observe the signal in the layer other than the surface layer, it is necessary to form a key in the integrated circuit chip, and there was a problem in that the cost of the integrated circuit chip increases considerably.
On the other hand, the conventional fault diagnostic method which uses the electron beam cannot specify the exact location where the signal is to be observed, and signals at locations where the observation is originally unnecessary are also inevitably observed. As a result, there were problems in that it takes considerable time to specify the timing fault, and that it is difficult to utilize the conventional diagnostic method which uses the electron beam for the timing fault diagnosis from a practical point of view.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful timing fault diagnosis method and apparatus in which the problems described above are eliminated.
A first more specific object of the present invention is to provide a timing fault diagnosis method and apparatus which can diagnose, at a high speed, a timing fault of an integrated circuit chip in which a logic circuit is formed.
A second more specific object of the present invention is to provide a timing fault diagnosis method and apparatus which can diagnose, at a high speed, a timing fault of an integrated circuit chip in which a logic circuit is formed, without forming a hole in the integrated circuit chip, so that the cost of the integrated circuit chip can be reduced compared to the case where the hole is formed in the integrated circuit chip.
Still another object of the present invention is to provide a timing fault diagnosis method (1) for diagnosing a timing fault of an integrated circuit chip having a logic circuit formed therein, comprising the steps of: (a) obtaining fail information by applying a test pattern to an external input terminal of the integrated circuit chip; (b) extracting, from the logic circuit, a circuit which is to be subjected to a timing fault diagnosis, based on logic structure data of the logic circuit and the fail information; (c) creating a timing fault pattern by assuming a timing fault in each of elements having a possibility of generating a timing fault within the circuit which is to be subjected to the timing fault diagnosis; and (d) specifying an element which is assumed to generate the timing fault based on a timing fault diagnosis by comparing the timing fault pattern and the fail information. According to the timing fault diagnosis method (1) of the present invention, it is possible to specify the timing fault observation location to a specific location because the timing fault is diagnosed by comparing the fail information and the timing fault pattern and the element assumed to generate the timing fault is specified.
A further object of the present invention is to provide a timing fault diagnosis method (2) conforming to the timing fault diagnosis method (1) above, wherein the step (b) comprises the substeps of: including in the circuit which is to be subjected to the timing fault diagnosis an external output terminal to which a timing fault propagates; including in the circuit which is to be subjected to the timing fault diagnosis a circuit on an upstream side along a signal path when viewed from the external output terminal to which the timing fault propagates; and including in the circuit which is to be subjected to the timing fault diagnosis a circuit on a downstream side of a signal path when viewed from an external input terminal within the circuit on the upstream side when viewed from the external output terminal to which the timing fault propagates. According to the timing fault diagnosis method (2) of the present invention, it is possible to efficiently determine the circuit which is to be subjected to the timing fault diagnosis, in addition obtaining effects similar to those obtainable by the timing fault diagnosis method (1).
Another object of the present invention is to provide a timing fault diagnosis method (3) conforming to the timing fault diagnosis method (1) above, wherein the step (c) creates the timing fault pattern by always assuming that the timing fault occurs when input data applied to the element assumed to generate the timing fault undergoes a transition. According to the timing fault diagnosis method (3) of the present invention, it is possible to create a timing fault pattern by taking into consideration the fuzziness of the timing fault generation, and the element assumed to generate the timing fault can be specified with a high accuracy, in addition obtaining effects similar to those obtainable by the timing fault diagnosis method (1).
Still another object of the present invention is to provide a timing fault diagnosis method (4) conforming to the timing fault diagnosis method (1) above, wherein the step (c) measures in advance a standard value and a margin with respect to a timing operation for each test pattern, and creates the timing fault pattern by assuming that the timing fault occurs only with respect to a specific test pattern of the element assumed to generate the timing fault. According to the timing fault diagnosis method (4) of the present invention, it is possible to further narrow down the elements assumed to generate the timing fault as compared to the timing fault diagnosis method (3) above, and the element assumed to generate the timing fault can be specified more accurately as compared to the timing fault diagnosis method (3), in addition obtaining effects similar to those obtainable by the timing fault diagnosis method (1).
A further object of the present invention is to provide a timing fault diagnosis method (5) conforming to the timing fault diagnosis method (

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