Timing edge forming circuit for IC test system

Details Timing edge forming circuit for IC test system Timing edge forming circuit for IC test system

1997-12-29

2000-02-29

Hua, Ly V.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714738, 713500, G06F 104

Patent

active

060322829

ABSTRACT:
A timing edge forming circuit includes a pattern generator for generating address data, a rate signal and pattern data, a first logic delay circuit for generating first delay time data by the address data wherein the first delay time data includes a first multiple delay time which is an integer multiple of one cycle of the clock signal and a first fractional delay time which is smaller than one cycle of the clock signal, and for sending an enable signal in synchronism with the clock signal which is delayed by the first multiple delay time and the first fractional delay time, a logic delay control circuit for adding the first fractional delay time to skew data to form second delay time data, a second logic delay circuit for providing a second multiple delay time in the second delay time data which is an integer multiple of one cycle of the clock signal to the enable signal, and for producing a second fractional delay time which is smaller than one cycle of the clock signal, a variable delay circuits for providing a high resolution delay time to the delayed enable signal based on the second fractional delay time.

REFERENCES:
patent: 5491673 (1996-02-01), Okayasu
patent: 5528186 (1996-06-01), Imamura
patent: 5592659 (1997-01-01), Toyama et al.
patent: 5710744 (1998-01-01), Suda
patent: 5903745 (1999-05-01), Nakayama et al.

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