Timing control method for operating synchronous memory

Details Timing control method for operating synchronous memory Timing control method for operating synchronous memory

2005-08-09

2005-08-09

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C036S181000, C036S181000

Reexamination Certificate

active

06928013

ABSTRACT:
A timing control method for operating a synchronous memory. The synchronous memory has a local data bus, a signal amplification bus and a global data bus. The timing control method includes manipulating the local data bus, the signal amplification bus and the global bus such that a series of operations including pre-charging the local data buses, developing signals on the amplifier buses is performed evenly within one clock cycle. Amplifying and transferring local data to global data is moved to next cycle and hid within the local data pre-charging period.

REFERENCES:
patent: 5835443 (1998-11-01), Fujita
patent: 6480423 (2002-11-01), Toda et al.
patent: 6483770 (2002-11-01), Noh et al.
patent: 6499111 (2002-12-01), Mullarkey

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