Timing control for input/output testability

Details Timing control for input/output testability Timing control for input/output testability

2000-05-05

2003-06-24

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S815000

Reexamination Certificate

active

06584591

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to source synchronous techniques, and in particular to the addition of delay circuitry to a chip that uses source synchronous techniques to improve testability of the chip.
2. Description of the Related Art
Strobe signals are clock signals that are transmitted with data signals, either simultaneously or after a predetermined delay. The strobe signal is used to time-synchronize data appearing as input signals at a receiver from a driver (transmitter). The use of the strobe signal to indicate when data should be sampled avoids using a clock which is sent to both driver and receiver. If this latter technique is used, then the skew between the two versions of the clock (transmitter and receiver) must be added to the time that each bit is driven from the driver, slowing it down. Sending the clock along with the data eliminates this skew by using the transmitter's clock both to send the data and to send the strobe. Data transfers are referred to as source synchronous when the clock (or strobe) signal that latches the data is supplied by the same chip (a driver) that is driving the data. With source synchronous data transfers, the same process, temperature, and voltage variations affect both the data and clock timings, and a multi-chip system does not need additional timing margin to account for independent variation in these variables along the clock and data paths.
Source synchronous I/O techniques permit very high bandwidth per chip pin. Usage of these techniques, however, is limited because of the difficulty in testing such circuits. Source synchronous circuits are difficult to test because: (1) they operate very fast, requiring great precision in tester edge (a high-to-low or low-to-high transition in a digital signal) placement accuracy; and (2) critical output timings are measured from one output pin to another, rather than from a clock input pin to an output pin.
The need for high precision edge placement leads to the use of very expensive testers. Testers are designed to place and measure edges with respect to a clock signal that the tester provides to the chip being tested. This restriction greatly simplifies the design of the tester, but also greatly complicates measuring the timing parameters that are critical to source synchronous outputs. For a centered clocking driver, these parameters include the time after the strobe which data is valid (T
va
) and the time before the strobe which data is valid (T
vb
) T
vb
is to be compared to the setup time T
setup
(required short time of stability before an active clock edge) and T
va
is to be compared to the hold time T
hold
(required short time of stability after the active clock edge) of the receiver. Large values are desirable for T
va
and T
vb
, which are related to the minimum and maximum output delay.
Source synchronous data transfers may be effected with either a coincident clocking signal
10
or a centered clocking signal
12
, as shown in FIG.
1
. For both, it is desirable for a data signal
16
to be strobed in the centers
20
of their respective valid windows or cells
22
. In other words, it is desirable to have the rising and falling edges of a strobe signal be time coincident with the centers
20
. Both edges
14
a
and
14
b
of a strobe
14
are used to sample the data
16
in adjacent cells
20
, as illustrated in FIG.
1
. To do this with coincident clocking
10
, the receiver delays the incoming strobe
14
by one-quarter of a clock (strobe) cycle to properly latch (sample) the data
16
being received. On the other hand, with centered clocking
12
, the driver (not shown) needs to delay an outgoing strobe
18
by a quarter of a clock (strobe) cycle to sample with both edges
18
a
and
18
b
. In
FIG. 1
, the strobe
18
is shown already delayed by a quarter clock cycle. Coincident clocking
10
thus offers better driver power supply noise correlation between the strobe
14
and the data
16
, while centered clocking
12
allows for a much simpler receiver.
Referring to
FIG. 2
a
, a coincident clocking transmitter and receiver system
8
, which may be located on a semiconductor device, is shown. A transmitter
33
is a simple circuit, and the inclusion of a delay-locked loop (DLL)
32
in a receiver
30
compensates for a distribution delay (for instance, with an RC recruit) to a flip-flop
34
or a plurality of such flip-flops (i.e., because an RC distribution network
38
is included in the DLL
32
in the receiver
30
) at the same time that it generates a 90° phase shift of the incoming strobe signal
14
, as will be discussed below. On the other hand,
FIG. 2
b
shows a centered clocking transmitter and receiver system
9
, which may also be located on a semiconductor device. In the system
9
, a receiver
31
is a simple circuit, but, in contrast to the system
8
, the RC distribution delay for propagating a strobe signal
40
′ (≅14′) within the receiving chip
31
is not compensated because an RC distributed network
38
′ (like the one in the receiver
31
) is not included in the DLL
32
′ in the transmitter
35
.
The DLL
32
having the RC distribution network
38
in the receiver
30
and the DLL
32
′ not having the RC distribution network
38
′ in the transmitter
35
contribute, among other factors, to differences between analogous signals
50
a
and
50
a
′,
50
b
and
50
b
′,
14
and
14
′, and
40
and
40
′ within the respective DLL's
32
and
32
′, although both systems
8
and
9
will produce ideally substantially the same signal
40
.
Referring again to
FIG. 2
a
, the DLL
32
is coupled to a clock input port
37
of a latch
34
, for example, a flip flop (FF), and controls latching of the data signal
16
, which is input to the latch
34
through a data input port
39
of the latch
34
. The solid dots above and below the latch
34
indicate that there may be more than one latch
34
coupled to the DLL
32
(and
32
′) to receive delayed strobe signals, as will be discussed below. (Similarly, solid dots above and below a latch
41
in the transmitter
33
(and
35
) indicate that there may be more than one FF
41
coupled to the receiver
30
[and
31
]).
Although most of the following discussion is framed in terms of the coincident clocking signal
10
, it should be understood that the concepts involved apply equally well to driver circuits (e.g., the transmitter
35
in
FIG. 2
b
) that are used to generate the centered clocking signal
12
for source synchronous data transfer. The DLL
32
receives as an input signal the strobe signal
14
and includes a delay line
36
, the distributed RC network
38
, another distributed RC network
44
, a delay line
42
, a phase detector (PD)
48
, and a filter (e.g., an RC low pass filter)
52
, as shown in
FIG. 2
a
. The distributed RC network
44
is built to approximately match the distributed RC network
38
. Likewise, the delay line
42
is built to approximately match the delay line
36
. This is done to have the delay from signals
14
to
40
be approximately the same as the delay from signals
40
to
46
. A disadvantage to the centered clocking approach is that the delay across the network
38
′ cannot be fully compensated by just including a network like the network
44
in the driver
35
, because the RC distribution network
38
′ and the network like the network
44
would no longer be in the same chip, subject to the same process, voltage, and temperature variations. The DLL
32
is used to delay the strobe (or clock)
14
(i.e., the edges
14
a
and
14
b
) to provide a centered clock similar to the centered strobe signal
12
(see FIG.
1
). The delay will enable the data
16
to be sampled (latched) by the latch
34
in the centers
20
of their respective valid windows
22
. This ensures optimum (i.e., short) setup and hold times for the receiving latch
34
.
In an alternative implementation (not shown) having no DLL, it is possibl

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