Timing control for input/output testability

Details Timing control for input/output testability Timing control for input/output testability

1997-12-24

2000-07-04

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

327 2, 327 3, G01R 3128, G01R 2500, G01R 2900, H03D 1300

Patent

active

06085345&

ABSTRACT:
Circuitry added to chips that use source synchronous techniques reduces difficulties associated with testing the chips. The circuitry increases the ability to use source synchronous techniques for data transmission. The circuitry is implemented in a delayed-lock loop (DLL) in either a transmitter (driver) or a receiver. The DLL measures the phase difference between a strobe signal and a delayed strobe signal. The DLL can be externally controlled by a source selectable input which allows the delay of the delayed strobe signal to be varied to test T.sub.setup and T.sub.hold in the receiver without varying the timings of the strobe signal and the data signals supplied to the chips. A timing measurement circuit having the strobe signal, the delayed strobe signal, and reference signals as inputs may be used to calibrate the phase difference between the strobe signal and delayed strobe signal.

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Lee, et al. ISSCC92/ Session 10/ Voltage-Controlled Oscillators and Phase-Locked Loops/Paper 10.2, IEEE, 1992, p. 160-161.

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