Timing circuit for high speed memory

Details Timing circuit for high speed memory Timing circuit for high speed memory

1999-07-09

2002-06-04

Butler, Dennis M. (Department: 2182)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S503000

Reexamination Certificate

active

06401213

ABSTRACT:

BACKGROUND
The invention relates generally to computer system memories and more particularly, but not by way of limitation, to the control of data access operations in a computer memory system using synchronous dynamic random access memory devices.
There are a number of different types of integrated circuit memories commercially available. The most widely used type of memory is dynamic random access memory (DRAM). In a DRAM device, individual memory cells within a two-dimensional array are accessed by a combination of row address (often referred to as a page) and column address signals. Different types of DRAM devices provide different methods of reading data from and writing data to the memory array. In a page mode DRAM, for example, once a page has been addressed, any number of different memory cells within that page (i.e., memory cells having different column addresses) may be accessed sequentially without needing to readdress the already selected page. Another type of DRAM device is the extended data output (EDO) DRAM. In an EDO DRAM device, once a page has been selected and an initial column specified, additional columns may be automatically accessed (in a pre-determined manner) without having to provide additional column addresses on the memory's external address pins.
Many current computer systems require memory access rates beyond those supported by page mode and EDO DRAM devices. One approach to improved memory access performance was to synchronize the memory device with the computer system's master clock. This type of memory is known as synchronous DRAM (SDRAM).
Another technique for improving memory access speed is for the memory device to use a separate data clock signal (often referred to as a data strobe signal or, more simply, a data strobe) to facilitate memory read and write operations. Memories of this type receive and use a data strobe during memory write operations, and generate and transmit a data strobe during memory read operations. To further increase memory system throughput or bandwidth, many current memory devices transfer data on both the rising and falling edges of the data strobe signal. Examples of this latter type of DRAM include double data rate (4R), RAMBUS®, and Synclink (SLDRAM) memory devices. The 4R standard is available from the Joint Electron Device Engineering Counsel (JEDEC), as document JESD-21-C. The RAMBUS® standard is published by Rambus, Incorporated of Mountain View, Calif. The Synclink standard has been assigned the preliminary designation P1596.7 by the Microprocessor & Microcomputer Standards Committee (MMSC) of the Institute of Electrical and Electronics Engineers (IEEE).
While SDRAM, 4R, RAMBUS®, and SLDRAM technologies provide the promise of increased memory system bandwidth, is also places severe constraints on the memory controller which coordinates the transfer of data between the memory and the computer system proper (e.g., a computer system's central processing unit). For example, the high data transfer rates supported by SDRAM devices mean that operational margins (e.g., the tolerance or variability between the data strobe and data signals) are measured in picoseconds (10
−12
seconds) rather than nanoseconds (10
−9
seconds) as in prior memory devices. Thus, it would be beneficial to provide a mechanism to maintain a precise clocking window for data access operations in high speed synchronous memory devices.
SUMMARY
In one embodiment the invention provides a timing circuit to adjust a data strobe signal received from a synchronous memory. The circuit includes a delay circuit to adjustably delay the data strobe signal and to generate a delayed data strobe signal, a clock capture register to sample the delayed data strobe signal and to generate a sampled clock signal, a data capture register to sample a read data signal from the synchronous memory and to generate a sampled data signal, and an analysis circuit to determine a timing relationship between the sampled clock signal and the sampled data signal and to adjust the delay circuit based on the determined timing relationship. By way of example, the determined timing relationship may be used to delay the read data strobe signal so that it transitions (e.g., from a low state to a high state) in the middle of the data signal's data eye. The timing circuit may, for example, be implemented as a separate memory control/monitoring device, or incorporated within an existing computer system memory controller.
In another embodiment, the invention provides a method to adjust a data strobe signal. The method includes receiving a read data strobe signal and a data signal from a synchronous memory device during a memory read operation, determining a timing characteristic between the read data strobe signal and the data signal, and delaying the read data strobe signal based on the measured timing characteristic. The method may be stored in any media that is readable and executable by a computer system. Alternatively, the method may be embodied in a custom designed hardware device such as an application specific integrated circuit, or implemented as a combination of software (computer executable instructions) and hardware.


REFERENCES:
patent: 4965884 (1990-10-01), Okura et al.
patent: 5926838 (1999-07-01), Jeddeloh
patent: 5978891 (1999-11-01), Takeda
patent: 6052329 (2000-04-01), Nishino et al.
patent: 6122688 (2000-09-01), Barth et al.

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