Timing circuit

Details Timing circuit Timing circuit

1998-03-13

2002-12-17

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S175000

Reexamination Certificate

active

06496552

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a timing circuit of an optical receiver in a high-speed optical communication system and, more particularly, to a timing circuit for generating a clock signal which indicates a timing for discriminating a received data signal.
The optical receiver in a high-speed optical communication system converts a data waveform which is distorted during transmission or a data waveform carrying noise into a clean waveform, in other words, executes what is called data regeneration. In such data regeneration, the optical receiver generates a clock signal by using a received data signal, and a discriminating portion reproduces data on the basis of the timing with which the clock signal is generated.
FIG. 19
shows an example of an optical receiver in an optical communication system. The reference numeral
1
represents an optoelectric conversion circuit for converting an optical signal into an electric signal,
2
an equalizing amplifier for equalizing and amplifying a data signal of, for example, 10 Gbps which is output from the optoelectric conversion circuit
1
,
3
a timing circuit for extracting a clock signal, which has a frequency same as that of the bit rate, from the data signal received, and
4
a discriminating circuit for discriminating the data signal by using the clock signal which is output from the timing circuit
3
. The optical signal transmitted through an optical fiber is converted by the optoelectric conversion circuit
1
into an electric signal, and equalized and amplified by the equalizing amplifier
2
. The timing circuit
3
extracts a clock signal from the equalized waveform and triggers the discriminating circuit
4
. The discriminating circuit
4
judges whether the equalized waveform is “0” or “1” at the point of time of sampling, and restores the original code pulse. Since there is a change in the delay time in the transmission line or the like, the discriminating circuit
4
is triggered by a clock signal which is synchronous with the data signal received.
In optical communication, an NRZ code, an RZ code, etc. is used as a transmission line code. In an optical communication apparatus of not less than 600 Mbps, an NRZ code in which the bands required for the electric circuit and the optical device are not strict is generally used. When an NRZ code is used, since a data signal contains no clock component, it is necessary to generate a clock signal by processing the data signal. A conventional timing circuit of an optical receiver for generating such a clock signal has either (1) a structure (
FIG. 20
) using a timing filter or (2) a structure (
FIG. 21
) using a PLL.
FIG. 20
shows the structure of a timing circuit using a timing filter. The timing circuit is composed of a nonlinear extractor
110
for detecting the rising edge and the falling edge of an input data signal, a bandpass filter
111
having a center frequency identical with the bit rate of the data signal, and a limiting amplifier
112
as a narrow band amplifier. The nonlinear extractor
110
includes a branching circuit
110
a
for branching a data signal in two directions, a delay circuit
110
b
for delaying a first branched data signal by a predetermined time (½ of the time equivalent to 1 bit), and an EXOR (Exclusive OR) circuit
110
c
for executing an exclusive OR operation of the second branched data signal and the output signal of the delay circuit
110
b
and generating an edge signal having a pulse at the rising edge and the falling edge of the data signal.
FIG. 22
shows an operating waveform. The EXOR circuit
110
c
detects the rising edge and the falling edge of the data signal and generates a pulse, the bandpass filter
111
extracts the clock component having the same frequency as that of the bit rate of the data signal, and the limiting amplifier
112
amplifies the clock component to a predetermined amplitude. Herein, the structure of the nonlinear extractor
110
having a combination of a differentiating circuit and a full-wave rectifier has also been proposed.
FIG. 21
shows the structure of a timing circuit using a PLL. The timing circuit is provided with a phase detector
121
for comparing the phases of a data signal and a clock signal and outputting the phase difference, a level converter
122
for converting the output level of the phase detector
121
, a loop filter
123
for smoothing the voltage signal corresponding to the phase difference which is output from the level converter
122
, and a voltage controlled oscillator (VCO)
124
for generating a clock signal having the frequency corresponding to the output of the loop filter
123
. As examples of the structure of the phase detector
121
, those shown in
FIGS. 23 and 24
have been proposed.
The phase detector
121
shown in
FIG. 23
compares the phase of a data signal DATA with the phase of a clock signal both at the rising edge and the falling edge of the data signal DATA, synthesizes the phase differences of the data signal at the rising edge and the falling edge, and executes PLL control. The phase detector
121
is provided with two D flip flops (D-FFs)
201
,
202
which function as phase detectors, an inverting gate
203
for inverting the logic of the data signal DATA and an adder
204
for adding the outputs of the D-FFs
201
,
202
.
The D-FF stores the level (“1” or “0”) of the clock signal CLOCK input to a data input terminal (terminal D) at the rising edge of each data signal DATA, *DATA input to a clock input terminal (terminal C), and holds the level until the next data signal rises. Therefore, when the phase of the clock signal CLOCK lags behind that of the data signal DATA, as shown in (1) of
FIG. 25
, the D-FF outputs a low-level (E
L
) signal D-FF out. On the other hand, when the phase of the clock signal CLOCK leads that of the data signal DATA, as shown in (2) of
FIG. 25
, the D-FF outputs a high-level (E
H
) signal D-FF out.
In this manner, the D-FF
201
outputs a signal corresponding to the phase of the clock signal at the rising edge of the data signal, while the D-FF
202
outputs a signal corresponding to the phase of the clock signal at the falling edge of the data signal. The adder
204
synthesizes these signals and outputs a phase detection signal PDS. The timing circuit having a PLL structure controls the phase of the clock signal so that the phase detection signal PDS has a preset level. For example, when the duty of the data signal varies to less than 100%, the rising edge of the data signal lags behind that of the clock signal and the falling edge of the data signal leads that of the clock signal. The phase detector
121
outputs the phase detection signal PDS which corresponds to the difference between the amount of lag and the amount of lead and the timing circuit outputs the clock signal CLOCK so that the amount of lag may be equal to the amount of lead.
The phase detector shown in
FIG. 24
detects the rising edge and the falling edge of a data signal DATA and compares the phases of a rising edge signal EGU and a falling edge signal EGD with the phase of a clock signal CLOCK. The phase detector is provided with an edge detector
251
and a D-FF
252
. The D-FF
252
outputs the level of the clock signal CLOCK as a phase detection signal PDS when the rising edge signal EGU and the falling edge signal EGD are produced. Since the phase detector is provided with the edge detector
251
, the same operation as that of the phase detector shown in
FIG. 23
is carried out with only one D-FF.
FIG. 26
is an explanatory view of the relationship between the phase difference &thgr; between the clock signal CLOCK and the data signal DATA and the output (phase detection signal PDS) of the phase detector. In this drawing, the duty of the data signal DATA is 100%, and the phase of the data signal DATA leads the phase of the clock signal CLOCK. The word “duty” will be defined strictly later, but briefly speaking, when the bit rate is f(=1/T), the duty is the ratio of the period T
1
of a data signal “1” and T. When

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