Timing analysis method for PLLS

Details Timing analysis method for PLLS Timing analysis method for PLLS

1997-09-26

1999-08-31

Kizou, Hassan

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

327147, 327156, 713400, G06F 300

Patent

active

059448342

ABSTRACT:
A method of analyzing timing differences for common path pessimism removal for a circuit containing a locked loop which controls at least two legs of a clock tree is provided. The method comprises the steps of computing the early and late mode delays for the locked loop; computing the early and late mode delays for delay segments in the circuit; identifying delay segments in the feedback path which control the locked loop; and adjusting the early and late mode delays for the delay segments in the feedback path based upon the type of feedback control used in the circuit.

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