Timing adjustment circuit for semiconductor test system

Details Timing adjustment circuit for semiconductor test system Timing adjustment circuit for semiconductor test system

1999-07-19

2001-07-17

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S032000, C324S612000

Reexamination Certificate

active

06263463

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a timing adjustment circuit for a semiconductor test system, and more particularly, to a timing phase adjustment circuit to adjust, within a short period of time, the timing differences between a plurality of test stations for simultaneously testing a plurality of IC devices in parallel.
BACKGROUND OF THE INVENTION
In testing a semiconductor device by a semiconductor test system, the semiconductor test system provides test signals to the semiconductor device under test and compare the resulting output of the device under test with expected data to determine whether the semiconductor device works correctly or not. Since the modern semiconductor device, such as an LSI (large scale integrated circuit), has a large number of input-output pins, a semiconductor test system also has a large number of test channels corresponding to the pins of the semiconductor device to be tested.
In the semiconductor test industry, it is a common practice to test a plurality of semiconductor devices which have a relatively small number of pins by a semiconductor test system in parallel at the same time. One of the reasons is that a semiconductor test system has a large number of test channels to test a semiconductor device having a large number of pins, it is advantageous to divide the test channels to form a plurality of test stations to test a plurality of semiconductor devices at the same time to increase the test efficiency. In testing a plurality of IC devices at the same time by a plurality of test stations, the timings of the test signals among the test stations must be the same, i.e, the timing differences between the test stations must be adjusted to be zero.
FIG. 4
is a block diagram showing a structure of conventional semiconductor test system for testing a plurality of semiconductor devices in parallel at the same time by a plurality of test stations. For convenience of explanation, the example of
FIG. 4
is to test two semiconductor devices and shows a test structure corresponding to only one pin P
1a
and P
1b
of the two respective semiconductor devices, DUT(a) and DUT(b) to be tested placed on the test stations ST
1
and ST
2
. Thus, it should be noted that similar circuit arrangements are also provided for other pins of DUT(a) and OUT(b) in the actual test system.
The system of
FIG. 4
includes a pattern generator
31
, a timing generator
32
, a wave formatter
33
, variable delay circuits
34
a
and
34
b
, drivers
35
a
and
35
b
, analog comparators
36
a
and
36
b
, and logic comparators
38
a
and
38
b
. The pattern generator
31
generates a test signal and expected data. The test signal is provided to the timing generator
32
where the timing of the test signal is determined. The test signal is wave shaped by the wave formatter
33
such as in an RZ waveform or an NRZ waveform. The test signal from the wave formatter
33
is provided to the drivers
35
a
and
35
b
through the variable delay circuits
34
a
and
34
b
. Thus, the test signal is commonly applied to the pins P
1a
of DUT(a) and P
1b
of DUT(b).
The outputs of the DUT(a) and DUT(b) are compared with reference voltages (not shown) by the analog comparators
36
a
and
36
b
by the timings of strobe signals Sb. The outputs of the analog comparators
36
a
and
36
b
are provided to the logic comparators
38
a
and
38
b
whereby compared with the expected data from the pattern generator
31
. In this arrangement, prior to the actual test of DUT(a) and DUT(b), the timing of the test signals at the pin P
1a
and P
1b
must be precisely adjusted.
To adjust the timings between the test stations ST
1
and ST
2
, in the conventional semiconductor test system, delay times of the variable delay circuits
34
a
and
34
b
are adjusted by monitoring the timing at the inputs of DUT(a) and DUT(b). Typically, such adjustment of the timing phase is carried out station by station with the use of a test instrument such as an oscilloscope.
In this conventional technology, since the timing in each of the test stations is manually adjusted, the time required for such adjustment increases with an increase of the number of test stations and the number of pins of the devices to be tested. Further, since the variable delay time circuit in each of the station is to adjust the delay time common to all of the stations, the range of varying the delay time is large, which requires many circuit components to realize such range of delay times. Moreover, since the timing adjustment is carried out manually, such adjustment may involve errors such as reading errors caused by an operator.
SUMMARY OF THE INVENTION
It is therefore, an object of the present invention to provide a timing phase adjustment circuit for a semiconductor test system which is capable of automatically adjusting timing differences between a plurality of test stations in a short period of time for testing a plurality of semiconductor devices at the same time.
It is another object of the present invention to provide a timing phase adjustment circuit for a semiconductor test system which is capable of automatically adjusting timing differences between a plurality of test stations while decreasing the circuit components required for variable delay circuits in the semiconductor test system.
It is a further object of the present invention to provide a timing phase adjustment circuit for a semiconductor test system which is capable of automatically adjusting timing differences between a plurality of test stations with high accuracy without involving errors by a user.
The timing adjustment circuit is used for a semiconductor test system having a plurality of test stations for testing a plurality of semiconductor devices in parallel at the same time. The timing adjustment circuit of the present invention is to adjust a timing phase difference between the test stations prior to the testing by including a unique feedback circuit.
The timing adjustment circuit of the present invention includes:
a wave formatter for commonly providing a test signal for adjusting the timing phase difference to the test stations;
a first variable delay circuit connected to an output of the wave formatter;
a plurality of second variable delay circuits each of which is connected to one of the plurality of test stations; a first data latch for holding delay data for the first variable delay circuit when timings in the plurality of test stations match one another;
a plurality of second data latches for separately holding delay data for the plurality of second variable delay circuits; a counter for generating the delay data by counting a system clock, higher bits of the delay data being provided to the first variable delay circuit through the first data latch and lower bits of the delay data being provided to the plurality of second variable delay circuits through the plurality of second data latches;
a lower bit ANO circuit for detecting a state in which all of the lower bits of the delay data are in the same logic state;
a detection circuit for detecting a signal arrival in each of the plurality of test stations based on the test signal; and
a delay data control circuit to send a latch command signal to each of the second data latches when receiving a detection signal indicating that the signal arrival in one of the test stations from the detection circuit, the delay data control circuit sending latch command signals to the first data latch and all of the second latches when receiving detection signals indicating that signal arrivals in all of the test stations occur within the same cycle of the system clock.
According to the present invention, the timing phase adjustment circuit for a semiconductor test system automatically adjusts timing differences between a plurality of test stations in a short period of time for testing a plurality of semiconductor devices at the same time. Since the procedure of adjusting the timing phase is done automatically, the timing adjustment will be completed with high accuracy without involving errors caused by a user. Fur

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