Time to digital converting circuit and related method

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

Reexamination Certificate

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C327S290000

Reexamination Certificate

active

07872602

ABSTRACT:
A TDC circuit includes: a first delay circuit, including at least one first delay stage for delaying a first input signal to generate a first output signal; a second delay circuit, including at least one second delay stage for delaying a second input signal to generate a second output signal; a first counter, for computing the first output signal to generate a first counter value; a second counter, for computing the second output signal to generate a second counter value; and a comparator, for comparing the first counter value and the second counter value to generate a comparing result signal; wherein the first delay stage has a larger delay amount than the second delay stage, the first counter starts before the second counter, and the comparator outputs the comparing result signal when the second counter value falls within a predetermined range of the first counter value.

REFERENCES:
patent: 6097674 (2000-08-01), Swapp
patent: 6754613 (2004-06-01), Tabatabaei et al.
patent: 2006/0284650 (2006-12-01), Kato
patent: 2010/0182186 (2010-07-01), Lin et al.

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