Time reduction of address setup/hold time for semiconductor...

Details Time reduction of address setup/hold time for semiconductor... Time reduction of address setup/hold time for semiconductor...

2011-02-15

2011-02-15

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189030, C365S189080, C365S063000, C365S051000, C365S194000

Reexamination Certificate

active

07889573

ABSTRACT:
In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.

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