Time multiplexed ratioed logic

Details Time multiplexed ratioed logic Time multiplexed ratioed logic

1997-03-17

1998-06-09

Westin, Edward P.

Electronic digital logic circuitry

Significant integrated structure, layout, or layout...

326 21, 326 98, 357206, H03K 1900, H01L 2500

Patent

active

057640840

ABSTRACT:
A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.

REFERENCES:
patent: 4771327 (1988-09-01), Usui
patent: 5138197 (1992-08-01), Kuwana
patent: 5510636 (1996-04-01), Murata
patent: 5581202 (1996-12-01), Yano et al.

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