Time data compression technique for high speed integrated...

Details Time data compression technique for high speed integrated... Time data compression technique for high speed integrated...

2001-03-22

2004-04-27

Tu, Christine T. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error/fault detection technique

C341S061000

Reexamination Certificate

active

06728931

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of testing of high speed memory devices and circuits. As IC technologies advance, the data rates for memory circuits and devices are increasing rapidly. Unfortunately, the speed of equipment designed to test these memories has not kept pace and tester limitations (or those of test environments such as wafer probe testing) restrict the capabilities currently available to the industry. In an attempt to deal with these limitations, current approaches have had to resort to multiple pass testing which serves to increase device test time. Alternatively, testing has had to be limited to relatively slow clock rate testing of high performance memories at a fraction of their intended operational speeds.
SUMMARY OF THE INVENTION
The present invention advantageously provides a time data compression technique which allows high speed memory devices and systems to be tested at full speed utilizing existing, slower speed test equipment. In operation, the memories may be “exercised” at their full intended data rate using a relatively slow tester or test environment without increasing test time or decreasing production throughput. The technique of the present invention can be utilized to effectively reduce the data rate by one half, one quarter or to any sub-multiple of the normal memory frequency without increasing time in test. In a particular embodiment, the present invention may be functional to convert double data rate (“DDR”) data to single data rate (“SDR”) to allow DDR memory devices to be more easily and effectively tested.
Through the use of the technique disclosed herein, data is initially sorted in time and then compared for a predetermined number of logic level “1s” or “0s” to be effectively compressed in time. This time compression allows high rate data streams to be tested at effectively slower rates. In particular representative embodiments of the present invention described herein, 2× or 4× data time compressions may be readily implemented although even higher compression factors may also be provided utilizing the techniques disclosed.
Particularly disclosed herein is a time data compression circuit comprising a sorting circuit for receiving an input data rate signal and providing corresponding first and second lower data rate signals at first and second outputs thereof. A compare circuit is coupled to the first and second outputs of the sorting circuit to produce a first output signal when the first and second lower data rate signals are at a same logic level and a second output signal when the first and second lower data rate signals are at an opposite logic level.
Further disclosed herein is a time data compression circuit comprising a first sorting circuit for receiving an input data rate signal and providing corresponding first and second lower data rate signals at first and second outputs thereof. A second sorting circuit is coupled to the first output of the first sorting circuit for providing third and fourth relatively lower data rate signals in response to the first lower data rate signal and a third sorting circuit is coupled to the second output of the first sorting circuit for providing fifth and sixth relatively lower data rate signals in response to the second lower data rate signal. A compare circuit is coupled to receive the third, fourth, fifth and sixth relatively lower data rate signals from the second and third sorting circuits, to produce a first output signal when the third, fourth, fifth and sixth relatively lower data rate signals are at a same logic level and a second output signal when the third, fourth, fifth and sixth relatively lower data rate signals are not all at said same logic level.
Also disclosed herein is a method for time data compression comprising the steps of receiving an input data rate signal, transforming the input data rate signal to first and second lower data rate signals, comparing the first and second lower data rate signals, outputting a first output signal when the first and second lower data rate signals are at a same logic level and outputting a second output signal when the first and second lower data rate signals are at an opposite logic level.
Still further disclosed herein is a method for time data compression comprising the steps of: receiving an input data rate signal, firstly transforming the input data rate signal to first and second lower data rate signals, secondly transforming the first and second lower data rate signals to third, fourth, fifth and sixth relatively lower data rate signals, comparing the third, fourth fifth and sixth relatively lower data rate signals, outputting a first output signal when the third, fourth fifth and sixth relatively lower data rate signals are at a same logic level and outputting a second output signal when the third, fourth fifth and sixth relatively lower data rate signals are not all at the same logic level.


REFERENCES:
patent: 5502752 (1996-03-01), Averbuch et al.
patent: 6195024 (2001-02-01), Fallon
patent: 6366588 (2002-04-01), Gans et al.
patent: 6366614 (2002-04-01), Pian et al.

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