Through silicon via lithographic alignment and registration

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S462000, C430S314000, C257SE21240

Reexamination Certificate

active

08039356

ABSTRACT:
A method of manufacturing an integrated circuit structure forms a first opening in a substrate and lines the first opening with a protective liner. The method deposits a material into the first opening and forms a protective material over the substrate. The protective material includes a process control mark and includes a second opening above, and aligned with, the first opening. The method removes the material from the first opening through the second opening in the protective material. The process control mark comprises a recess within the protective material that extends only partially through the protective material, such that portions of the substrate below the process control mark are not affected by the process of removing the material.

REFERENCES:
patent: 4978419 (1990-12-01), Nanda et al.
patent: 6521493 (2003-02-01), Alsmeier et al.
patent: 6610448 (2003-08-01), Sato et al.
patent: 6809005 (2004-10-01), Ranade et al.
patent: 6818524 (2004-11-01), Yang et al.
patent: 7381503 (2008-06-01), Smith et al.
patent: 7485965 (2009-02-01), Lanzerotti et al.
patent: 7510916 (2009-03-01), Chu
patent: 7723181 (2010-05-01), Liu et al.
patent: 2006/0091476 (2006-05-01), Pinnow et al.
patent: 2006/0234440 (2006-10-01), Wu et al.
patent: 2007/0018341 (2007-01-01), Hsieh et al.
patent: 2007/0035031 (2007-02-01), Jessen et al.
patent: 2007/0059871 (2007-03-01), Yamazaki
patent: 2007/0184355 (2007-08-01), Wallace et al.
patent: 2007/0190736 (2007-08-01), Liu et al.
patent: 2007/0224519 (2007-09-01), Sivakumar et al.
patent: 2008/0085599 (2008-04-01), Van Haren et al.
patent: 2009/0160009 (2009-06-01), Dietz et al.
patent: 2011/0111560 (2011-05-01), Purushothaman et al.
Yamazoe, et al., “Resolution Enhancement by Aerial Image Approximation with 2D-TCC,” Proceedings of SPIE, vol. 6730, Photomask Technology 2007, Sep. 18-21, 2007, pp. 67302H-1-67302H-12.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Through silicon via lithographic alignment and registration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Through silicon via lithographic alignment and registration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Through silicon via lithographic alignment and registration will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4301682

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.