Through-core self-test with multiple loopbacks

Details Through-core self-test with multiple loopbacks Through-core self-test with multiple loopbacks

2004-10-29

2008-03-18

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S734000, C714S716000

Reexamination Certificate

active

07346819

ABSTRACT:
An integrated circuit device having a test sequence generator, first and second transceivers and a test sequence analyzer. The test sequence generator generates a test data sequence in response to a test mode selection. The first transceiver receives the test data sequence from the test sequence generator and is configured in a loopback mode to transmit and receive the test data sequence. The second transceiver receives the test data sequence received by the first transceiver and is configured in a loopback mode to transmit and receive the test data sequence. The test sequence analyzer determines whether the test data sequence received by the second transceiver matches the test data sequence generated by the test sequence generator.

REFERENCES:
patent: 5630056 (1997-05-01), Horvath et al.
patent: 7051252 (2006-05-01), Smith et al.
patent: 7082557 (2006-07-01), Schauer et al.
patent: 2002/0040459 (2002-04-01), Watanabe et al.
patent: 2004/0068683 (2004-04-01), Hoang et al.

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