Three-value input buffer circuit

Details Three-value input buffer circuit Three-value input buffer circuit

1994-10-26

1995-12-26

Westin, Edward P.

Electronic digital logic circuitry

Three or more active levels

With conversion

326 21, 326 58, 341 57, H03K 190948, H03K 1900

Patent

active

054791146

ABSTRACT:
A 3-value input buffer circuit is configured by a first N-channel MOS transistor whose source is connected to an input terminal, a first P-channel MOS transistor which is connected to the first N-channel MOS transistor, a first inverter whose input is connected to a drain of the first P-channel MOS transistor, a second P-channel MOS transistor whose source is connected to the input terminal, a second N-channel MOS transistor which is connected to the second P-channel MOS transistor, a second inverter which is connected to a drain of the second N-channel MOS transistor, and a voltage applying circuit which is constituted by P-channel MOS transistors and which applies a constant voltage to a gate of each of the first N-channel MOS transistor and the second P-channel MOS transistor. The first N-channel MOS transistor and the second P-channel MOS transistor are cut off when the input terminal is in an open state. Thus, the power consumption can be significantly suppressed.

REFERENCES:
patent: 5124590 (1992-06-01), Liu et al.
patent: 5194766 (1993-03-01), Sugawara
patent: 5373202 (1994-12-01), Armstrong, II

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