Three-transistor SRAM device

Details Three-transistor SRAM device Three-transistor SRAM device

2002-01-04

2003-09-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S185070

Reexamination Certificate

active

06621727

ABSTRACT:

RELATED FIELD
The present invention relates to Static Random-Access Memories (SRAM), which can typically be found in personal computers or portable electronics systems.
ART BACKGROUND
Modem computer memories are typically built with several types of chips, all of which have different properties. One of the memory types is Dynamic Random-Access Memories (DRAMs). DRAMs have the highest number of bits/chip (highest memory bit density), but with the disadvantage that they have to be “refreshed” in order not to lose their information, which is stored in a capacitor.
Another memory type is Static Random-Access Memories. SRAMs store the information in latches. Although they take more silicon area per bit than DRAMs, they have the advantage that they do not require to be refreshed. Since SRAMs store their information in latches, it always takes shorter read/write time than DRAMs.
A book by A. J. van de Goor, entitled TESTING SEMICONDUCTOR MEMORIES THEORY AND PRATICE, 1991, by John Wiley & Sons Ltd., England, provides ample background information about the computer memories such as DRAMs and SRAMs. This book is incorporated herein by this reference as though fully set forth herein.
There are generally three types of SRAM cell structures, as will be described below in connection with FIGS.
1
(
a
)-(
c
).
FIG. 2
provides a listing of symbols as commonly used by those skilled in the art of semiconductor devices.
A six-device SRAM cell is shown in FIG.
1
(
a
). It consists of the enhancement-mode NMOS transistors Q
1
, Q
2
, Q
5
and Q
6
; and the depletion-mode NMOS transistors Q
3
and Q
4
. Transistor Q
1
forms an inverter together with depletion-mode NMOS transistor Q
3
. This inverter is cross-coupled with an inverter formed by Q
2
and Q
4
, thus forming a latch. This latch can be accessed, for read and write operations, via the pass transistors Q
5
and Q
6
.
Addressing of cells is done using a two-dimensional addressing scheme consisting of a row and a column address. A row decoder (not shown) allows only one row of cells to be selected at a time by activating the word line (WL) of that particular row. Note that within the chip, a memory word is synonymous with a row. The WL is connected to all gates of the pass transistors of all cells in that row, and only one WL should be active at a time. The selection of a particular cell in a row is done under control of a column decoder (not shown), which activates the set of complementary bit lines (BLs) of that particular cell.
Data can be written by driving WL high and driving the lines BL and {overscore (BL)} with data with complementary values. Because the bit lines are driven with more force than the force with which the cell retains its information (the transistors driving the line BL and {overscore (BL)} are more powerful, i.e. they are larger than the transistors Q
1
and Q
2
), the cell will be forced to the state presented on the lines BL and {overscore (BL)}. In the case of a read operation, a particular row is selected by activating the corresponding WL. The contents of the cell on a row, accessed by the activated WL, are passed to the corresponding sense amplifiers via the BL and {overscore (BL)} lines. A data register can be loaded by selecting the outputs of the desired sense amplifiers under control of the column decoder.
As shown in FIG.
1
(
b
), the depletion loads Q
3
and Q
4
of FIG.
1
(
a
) have been replaced with resistors R
1
and R
2
in order to decrease silicon area usage and power dissipation of the cell. The resistors are made from polysilicon with a high resistivity, e.g. having a value of 1000G&OHgr;, causing an asymmetry in the logic “1” and “0” drive power of the latch. A logic “0” level is caused by a conducting transistor (Q
1
or Q
2
) which allows for a relatively low ohmic path. A logic “1” level is caused by a non-conducting transistor (Q
2
or Q
1
) and has to be maintained by the high ohmic polysilicon resistor, which is dimensioned such that it will be able to supply the relatively small leakage current of the non-conducting transistor (Q
2
or Q
1
).
As shown in FIG.
1
(
c
), the load devices of FIG.
1
(
a
) have been replaced with PMOS enhancement mode transistors Q
3
and Q
4
. This complementary use of both PMOS and NMOS transistors, commonly referred to as “CMOS,” further reduces the power requirements of the cell; except for some small leakage current, no power will be dissipated during the time the cell retains the stored logic value. The disadvantage of CMOS technology is that it requires more processing steps because of the presence of both NMOS and PMOS transistors.
While SRAMs have certain advantages over DRAMs in terms of having quicker access without the need to refresh, SRAMs generally require larger chip area than DRAMs. For example, one of the disadvantages of the circuit shown. in FIG.
1
(
c
) is that the chip area ends up having too many transistors. As shown in FIG.
1
(
c
),
6
transistors are required in one cell design, especially with both P-type and N-type transistors at same cell. Under the CMOS design methodology, as is well known, to prevent “latch-up,” which can burn out the devices, special “distance” and “isolation barrier” are required to separate the P-type transistors from the N-type transistors. Such distance and isolation barriers also require more chip space. While the circuit shown in FIG.
1
(
a
) is implemented with
6
transistors, all of them are N-type. As such, the problem of “latch-up” is of little concern for the circuit of FIG.
1
(
a
).
In FIG.
1
(
a
), however, the circuit has other disadvantages. While in data latch, one of the depletion mode transistors (Q
3
or Q
4
) with the latch-current forms a drain-to-source path. For example, while “drain” of Q
1
is in condition “high”, the “drain” of Q
2
is in “low”, and a latch current will flow from “drain” of Q
4
(“high”) to “source” of Q
4
(i.e. “drain” of Q
2
which is in “low”), and then flow through Q
2
from “drain” to “source”. As such, a constant supply current is required during the “stand by” condition. As such, the circuit of FIG.
1
(
a
) also has the disadvantages of requiring a large chip area and requiring large power consumption.
The circuit in FIG.
1
(
b
) is implemented with only 4 transistors in one cell, thus requiring smaller chip area. However, the resistors R
1
and R
2
will limit the current from Vcc to BL and {overscore (BL)}, and lower the sensitivity, as well as require more time to “read”. Also one of the resistors (R
1
or R
2
) with the latch-current during the stand by condition. For example, while the drain of Q
1
is High, the drain of Q
2
will be Low under latch occurrence. However, a stand-by current will flow from Vcc through R
1
to the drain of Q
2
, and then flow through Q
2
from drain to source which is Vss. The stand-by current will also cause power loss. Therefore, the circuit of FIG.
1
(
b
) still suffers from having lower read speed and lower read sensitivity, while still requiring large power consumption.
SUMMARY OF THE DISCLOSURE
Therefore, it is an object of the present invention to provide an SRAM cell with smaller chip area.
It is also an object of the present invention to provide an SRAM cell with more stabilized latch point voltage during date read operation.
It is yet another object of the present invention to provide an SRAM cell with lower power loss during write operation.
It is yet another object of the present invention to provide an SRAM cell which can retain data even when the power is turned off.
A three-transistor SRAM cell is disclosed. The SRAM cell has an NMOS with its source connected to a first voltage source and its substrate connected to a second voltage source. The drain of the NMOS is connected either a constant voltage source or a variable voltage source. An PMOS and the NMOS form a common node A. The source of the NMOS is connected to the source of the PMOS to form a common node B. A resister is connected between the nodes A and B. Another NMOS is connected between the node B and a bit line. The gate of this NMOS i

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