Three dimensional twisted bitline architecture for...

Details Three dimensional twisted bitline architecture for... Three dimensional twisted bitline architecture for...

2007-10-23

2007-10-23

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S156000, C365S207000

Reexamination Certificate

active

11160302

ABSTRACT:
A memory array of dual part cells has a pair of twisted write bitlines and a pair of twisted read bitlines for each column. The twist is made by alternating the vertical position of each bitline pair in each section of a column, with the result of generating common mode nose and of reducing differential mode noise.

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U.S. Appl. No. 10/604,994, Title: Multi-Port Memory Architecture, Kim, et al., filed Aug. 29, 2003.

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