Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-10
2001-02-06
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06185722
ABSTRACT:
BACKGROUND OF THE INVENTION
In deep sub-micron designs, the effect of wire capacitance on system performance is as important as, if not more so than, the gate delay. To accurately predict system performance, accurate extraction of resistance and capacitance parasitics is required. The capacitance of a wire is dependent not only on its length, width, and thickness, but also on the environment around the wire. The environment includes any adjacent or near wires and the substrate itself. As wire pitches become smaller, the effects on capacitance of adjacent lines can be as much as two times as compared to an isolated wire. It is therefore very important to take into account the environment of a wire when predicting its capacitance.
Historically, most chip-level capacitance extractors have used one of two methods to derive wire capacitance:
1) High level analysis based on gross assumptions about the amount of capacitance per length of wire. This method relies on an educated guess as to the amount of adjacent wire that might be present. This is sufficient when the environment of a conductor does not change significantly or when the capacitance of the interconnects is only a small contributor to the overall output load.
2) Detailed shapes based analysis of the design environment surrounding the wire under consideration. This method is very computer intensive. Accurate total capacitance extraction of large chips is presently not feasible with this approach due to data volume and computer execution time.
Previous solutions in the second category are design shape based. They have to calculate and store a large number of geometric interacting shapes, creating a large computational burden and an immense amount of output. An example is Avant!'s LPE extraction. The Avant! extractor uses design shapes to calculate the capacitances based on overlap areas distances and perimeters. This requires a large amount of data to be stored and processed.
Another solution in the second category, pattern recognition, can also take advantage of the regular structure of global wires. But the recognition mechanism on design shapes is not as efficient and the intermediate storage requirements are much more severe. The tables are huge; the search and the generation is very time consuming. Pattern recognition solutions are accurate but cannot handle wire extraction for a complete chip. ARCADIA from EPIC takes this approach.
Now, with narrowly spaced five and six levels of metal, the overall wire capacitance is larger and varies by a factor of two depending upon neighboring wires. Effects of neighboring conductors have become the dominant contribution to the load in many critical nets and the hold time needed on many paths. Resolution of adjacencies becomes a critical part of accurate chip timing.
Therefore, method 1 is not a viable solution for these deep sub-micron technology designs because it doesn't take neighboring wires into account. Method 2 is not practical for large designs due to the data volume and computer execution time.
SUMMARY OF THE INVENTION
The invention takes advantage of the repetitive structure of the wiring and therefore does not need to calculate all these shapes present in a design. It also adds the capacitances along a net while they are generated, and so it does not need to store all this data, thus creating a huge advantage in efficiency.
This invention reduces the complexity of conductor environment, takes full advantage of the repetitive structure of automatic wiring, produces accurate results within ten percent of a full three dimensional finite element analysis and within ten percent as measured in hardware. It obtains, with its unique data structures and approximations, large improvements in runtime and data volume capacity over existing tools.
One object of this invention is to determine which wiring patterns are significant through a detailed analysis of the various topologies and to generate entirely inclusive, capacitance data tables based on this knowledge.
Another object of this invention is to provide an extraction tool which applies a searching technique to discover the environment around a section of wire and then does only one memory reference to obtain the entire capacitance for a one unit length section of the wire.
It is a further objective of this invention to provide a tool which models its environment based on a three dimensional yes
o boolean grid to accomplish full chip capacitance extraction without limiting the flexibility of handling any wire width as long as the wire spine is on the grid.
Yet another objective of this invention is a capacitance extraction tool that establishes a priority to the searches allowing the tool to stop searching when the first neighbors are encountered.
Yet another objective is to provide a capacitance extraction tool which partitions the capacitance data to ensure additivity of capacitance of one unit length wire pieces and avoid double counting of three dimensional effects.
Yet another objective is to provide resistance data tables based on the environment and a resistance extraction tool with the same capabilities as the capacitance extraction tool, but with respect to resistance.
Yet another objective of this invention is to produce RC data output from the extraction process, eliminating the need for elaborate post-processing steps.
A final objective of this invention is to calculate net to net coupling capacitance for use in various tools such as static timing analysis tools, simulation tools, and noise analysis tools.
REFERENCES:
patent: 4412240 (1983-10-01), Kikuchi et al.
patent: 5461579 (1995-10-01), Misheloff et al.
patent: 5510999 (1996-04-01), Lee et al.
patent: 5706206 (1998-01-01), Hammler et al.
patent: 5761080 (1998-06-01), DeCamp et al.
patent: 5828580 (1998-10-01), Ho
patent: 5838582 (1998-11-01), Mehrotra et al.
patent: 5896300 (1999-04-01), Raghavan et al.
patent: 5901063 (1999-05-01), Chang et al.
patent: 5923568 (1999-07-01), Oh et al.
patent: 5999726 (1999-12-01), Ho
Belkhale and Banerjee “Parallel Algorithms for VLSI Circuit Extraction,” IEEE Transactions on Computer-Aided Design, vol. 10, No. 5, May, 1991, p. 604-618.
Schaper et al. “Modeling and Experimental Verification of the Interconnected Mesh Power System (IMPS) MCM Topology,” IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, vol. 20, No. 1, Feb., 1997, p. 42-49.
Wehn and Glesner “A New Approach to Timing Driven Partitioning of Combinational Logic,” IEEE, 1991, p. 106-111.
Lin and Kompa “FET Model Parameter Extraction Based on Optimization with Multiplane Data-Fitting and Bidirectional Search—A New Concept,” IEEE Transactions on Microwave Theory and Techniques, vol. 42, No. 7, Jul., 1994, p. 1114-1121.
Darden Laura Rohwedder
Engel James John
Habitz Peter Anton
Livingstone William John
Mainiero Daniel Joseph
Garbowski Leigh Marie
International Business Machines - Corporation
Kotulak Richard M.
Lintz Paul R.
LandOfFree
Three dimensional track-based parasitic extraction does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Three dimensional track-based parasitic extraction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Three dimensional track-based parasitic extraction will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2590213