Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-01-28
2002-09-10
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S686000
Reexamination Certificate
active
06448661
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor packaging technology and, more particularly, to a three-dimensional, multi-chip package with chip selection pads and a manufacturing method thereof.
2. Description of the Related Art
In order to satisfy the pressing demands for increased integration and multi-functionality, various three-dimensional multi-chip packages have recently been developed. A conventional three-dimensional multi-chip package is manufactured as described below. After manufacturing a wafer and separating the wafer into a plurality of individual chips, the chip is attached and electrically connected to the substrate, and is encapsulated with a molding resin to produce a package. Then, a multi-chip package is obtained by stacking the packages.
These multi-chip packages employ a lead frame, or a substrate such as a tape circuit board or a printed circuit board. Various interconnection methods such as a wire-bonding method, tape automated bonding (TAB) method, or flip chip-bonding method, are employed to establish electrical connection between the chip and the substrate.
The multi-chip packages formed by stacking a plurality of packages are disclosed in U.S. Pat. Nos. 4,982,265, 4,996,583, 5,172,303, 5,198,888, 5,222,014, 5,247,423, 5,313,096, 5,783,870 and 6,072,233. However, these multi-chip packages are manufactured using complex processes. Moreover, these multi-chip packages have much bigger sizes than the standard chip, thereby reducing the mounting density on the external apparatus. Further, since the multi-chip packages employ substrates, they cause long signal transmission routes and thereby signal delay results.
While three-dimensional multi-chip packages on wafer-level or chip-level are disclosed in U.S. Pat. Nos. 4,394,712, 4,807,021, 4,897,708, 4,954,875, 5,202,754, 5,229,647 and 5,767,001. These multi-chip packages have the advantage of simple structures, smaller sizes, and simple manufacturing processes. Further, a multi-chip package at the wafer-level prevents signal delay. However, this technique is applied only to non-memory devices such as Application Specific Integrated Circuit (ASIC) or to multi-chip packages with multiple functions by stacking different types of chips.
Generally, multi-chip packages are classified into two types. One is a multi-chip package formed by stacking different types of chips, thereby achieving multi-functionality. The other is a multi-chip package formed by stacking the same types of chips, thereby improving memory capacity.
In order to improve memory capacity by stacking the same types of chips, there must be a chip selection mechanism to operate the desired chip. Therefore, each memory chip comprises a chip selection terminal. For example, in case of a DRAM chip, the Row Address Strobe (RAS), Column Address Strobe (CAS) or Chip Selection Pin (CSP) is used as the chip selection terminal. By selectively transmitting electronic signals to the specific chip selection terminal corresponding to the desired chip of the multi-chip package, the desired chip is selected for operation. Other non-selecting terminals of the memory chips in the multi-chip package are commonly connected together, but the chip selection terminal for each individual chip are isolated and connected to an external electronic component.
The conventional technique for separating the chip selection terminals of each chip from one another is disclosed in the above-described multi-chip package. That is, the chip selection terminal of each chip is connected to an external electronic component through connection wirings formed on a substrate of the package. Therefore, in order to separate the chip selection terminal of each chip from one another, each substrate should comprise a connection wiring configuration different from the other substrates, thereby increasing the production cost and reducing productivity.
The drawbacks are prevented by a conventional technique disclosed in U.S. Pat. No. 5,995,379. In this patent, the chip selection terminal of each chip is connected to external electronic components by a substrate with the same connection wiring configuration as the substrate of the other chips. However, since this technique is applied to a multi-chip package by stacking packages, it requires substrates on which connection wirings are formed. Therefore, this technique also has the previously described drawbacks of stacked, multi-chip packages such as large package size, reduced mounting density, complex manufacturing processes, and signal delay.
SUMMARY OF THE INVENTION
The present invention increases memory capacity by providing a multi-chip package formed by stacking at least two of the same types of chips.
The present invention provides a multi-chip package at the wafer-level, thereby reducing package size, increasing mounting density, and preventing signal delay.
The present invention separates the chip selection terminal of each chip from one another via chip selection pads formed at the chip-level. The present invention simplifies the manufacturing process of the multi-chip package.
According to one embodiment, a three-dimensional, multi-chip package is formed by stacking a number (N) of semiconductor integrated circuit chips. Each chip comprises an integrated circuit die, a chip selection terminal, a number (N−1) of chip selection pads, an insulation layer, a number (N−1) of metal wirings, upper connection terminals, lower connection terminals, and trench wirings.
The chip selection terminal and the chip selection pads are formed on an upper surface of the die, and the chip selection pads are proximate to the chip selection terminal. The insulation layer is formed on the upper surface of the die, and the metal wirings are formed within the insulation layer and connected to the chip selection pads. The upper connection terminals are formed on the insulation layer and connected to the metal wiring. The lower connection terminals are formed on the lower surface of the die, and each of the lower connection terminals is connected to a corresponding one of the chip selection terminal and the chip selection pads. The trench wirings extend through the die, and connect the chip selection terminal and the chip selection pads to the lower connection terminals.
Among the chip selection pads, a first chip selection pad next to the chip selection terminal is connected to the upper connection terminal formed above the chip selection terminal, and the (N−1)th chip selection pad is connected to the upper connection terminal formed above the (N−2)th chip selection pad. The individual chips are stacked by attaching the upper connection terminals of a lower chip to the lower connection terminals of an upper chip. The chip selection terminal of each chip is connected to a corresponding one of the lower connection terminals of a lowermost chip.
Further, the present invention provides a method of manufacturing a chip-level, three-dimensional, multi-chip package by stacking a number (N) of semiconductor integrated circuit chips.
In accordance with the method of the present invention, a chip selection terminal and a number (N−1) of chip selection pads close to the chip selection terminal are formed on the upper active surface of the chip, and a plurality of trenches from the chip selection terminal and the chip selection pads are formed within the chip. Then, trench wirings are formed by filling the trenches with a conductive material, and a number (N−1) of first metal wirings formed along the upper surface of the chip, each of the first metal wirings are connected to a corresponding one of the chip selection pads. A first insulation layer is formed on the upper surface of the chip and the first metal wirings, and a plurality of upper connection terminals connected to the first metal wirings are formed on the first insulation layer. The lower surface of the chip is grinded so that the trench wirings are exposed through the lower surface of the chip. A plurality of lower connecti
Chung Myung-Kee
Kang In-Ku
Kang Sa-Yoon
Kim Hyeong-Seob
Lee Kwan-Jai
Clark Sheila V.
Marger Jonson & McCollom, P.C.
Samsung Electornics Co., Ltd.
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