Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-12-22
2003-07-08
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06591394
ABSTRACT:
BACKGROUND
Conventional memory design assumes that high-speed read access is an important goal. Accordingly, conventional two-dimensional semiconductor memories, such as DRAMs, SRAMs, ROMs, EEPROMs, and Flash memories, are designed to maximize speed. These memories achieve fast access time at the expense of large chip area and high chip cost. To increase circuit performance, some conventional memory devices store data bits and error checking and correcting (ECC) bits near each other to reduce the portions of the memory device that are activated. By localizing the data bits and ECC bits within a region of the memory device, more than one bit is retrieved from a single activated row line, thereby reducing the power consumed by a memory cycle. While localizing data bits and ECC bits within a region of the memory device can increase circuit performance, such a data distribution scheme can result in non-correctable memory errors. Most ECC circuitry is capable of correcting only single-bit errors within a given word. For example, with a Hamming (72, 64) code scheme, only a single-bit error in 72 bits of stored data can be corrected. Storing data bits and ECC code bits in physically-contiguous regions of the memory array increases the probability that a media defect will affect more than a single bit in any data word, thereby increasing the probability of a non-correctable error.
In contrast to conventional memory arrays, three-dimensional memory arrays, such as those described in U.S. Pat. No. 6,034,882 to Johnson, provide important economies in terms of reduced size and associated reductions in manufacturing cost. Manufacturing defects or age-related fatigue of such high bit-density memory devices can raise the probability of bit errors. Accordingly, the disadvantages associated with storing data bits and ECC code bits in physically-contiguous regions of the memory array can be more exaggerated in three-dimensional memory arrays as compared to conventional memory arrays.
SUMMARY
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims.
By way of introduction, the preferred embodiments described below provide a three-dimensional memory array and method for storing data bits and ECC bits therein. In one preferred embodiment, a three-dimensional memory array of the type that includes multiple vertically-stacked layers of memory cells is provided. The three-dimensional memory array comprises a plurality of memory cells arranged in a plurality of physically-independent sub-arrays, and data bits and error checking and correcting (ECC) bits of a word are stored in respective ones of the physically-independent sub-arrays. By spatially diffusing data bits and ECC bits from a word, the likelihood of multiple-bit errors within the word is reduced. This is advantageous since most ECC circuitry is capable of correcting only single-bit errors within a given word. Other preferred embodiments are disclosed.
The preferred embodiments will now be described with reference to the attached drawings.
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Cleeves James M.
Johnson Mark G.
Lee Thomas H.
Brinks Hofer Gilson & Lione
De'cady Albert
Lamarre Guy
Matrix Semiconductor Inc.
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