Metal treatment – Barrier layer stock material – p-n type – With non-semiconductive coating thereon
Reexamination Certificate
2005-06-14
2005-06-14
Fourson, George (Department: 2823)
Metal treatment
Barrier layer stock material, p-n type
With non-semiconductive coating thereon
C257S684000
Reexamination Certificate
active
06905557
ABSTRACT:
A device integration method and integrated device. The method includes the steps of polishing surfaces of first and second workpieces each to a surface roughness of about 5-10 Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1-10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies.
REFERENCES:
patent: 4829018 (1989-05-01), Wahlstrom
patent: 4962879 (1990-10-01), Goesele et al.
patent: 5087585 (1992-02-01), Hayashi
patent: 5089431 (1992-02-01), Slatter et al.
patent: 5196375 (1993-03-01), Hoshi
patent: 5266511 (1993-11-01), Takao
patent: 5272104 (1993-12-01), Schrantz et al.
patent: 5321301 (1994-06-01), Sato et al.
patent: 5362659 (1994-11-01), Cartagena
patent: 5376579 (1994-12-01), Annamalai
patent: 5380681 (1995-01-01), Hsu
patent: 5407856 (1995-04-01), Quenzer et al.
patent: 5441591 (1995-08-01), Imthurn et al.
patent: 5441911 (1995-08-01), Malhi
patent: 5459104 (1995-10-01), Sakai
patent: 5485540 (1996-01-01), Eda
patent: 5514235 (1996-05-01), Mitani et al.
patent: 5546494 (1996-08-01), Eda
patent: 5548178 (1996-08-01), Eda et al.
patent: 5561303 (1996-10-01), Schrantz et al.
patent: 5563084 (1996-10-01), Ramm et al.
patent: 5580407 (1996-12-01), Haisma et al.
patent: 5591678 (1997-01-01), Bendik et al.
patent: 5647932 (1997-07-01), Taguchi et al.
patent: 5650353 (1997-07-01), Yoshizawa et al.
patent: 5652436 (1997-07-01), Stoner et al.
patent: 5661316 (1997-08-01), Kish, Jr. et al.
patent: 5666706 (1997-09-01), Tomita et al.
patent: 5668057 (1997-09-01), Eda et al.
patent: 5672240 (1997-09-01), Stoner et al.
patent: 5698471 (1997-12-01), Namba et al.
patent: 5741733 (1998-04-01), Bertagnolli et al.
patent: 5747857 (1998-05-01), Eda et al.
patent: 5755914 (1998-05-01), Yonehara
patent: 5759753 (1998-06-01), Namba et al.
patent: 5763318 (1998-06-01), Bertin et al.
patent: 5766984 (1998-06-01), Ramm et al.
patent: 5771555 (1998-06-01), Eda et al.
patent: 5785874 (1998-07-01), Eda et al.
patent: 5821665 (1998-10-01), Onishi et al.
patent: 5849627 (1998-12-01), Linn et al.
patent: 5851894 (1998-12-01), Ramm
patent: 5872025 (1999-02-01), Cronin et al.
patent: 5877034 (1999-03-01), Ramm et al.
patent: 5877516 (1999-03-01), Mermagen et al.
patent: 5880010 (1999-03-01), Davidson
patent: 5902118 (1999-05-01), Hubner
patent: 5910699 (1999-06-01), Namba et al.
patent: 5920142 (1999-07-01), Onishi et al.
patent: 5982010 (1999-11-01), Namba et al.
patent: 5991989 (1999-11-01), Onishi et al.
patent: 6004866 (1999-12-01), Nakano et al.
patent: 6018211 (2000-01-01), Kanaboshi et al.
patent: 6087760 (2000-07-01), Yamaguchi et al.
patent: 6120917 (2000-09-01), Eda
patent: 6146992 (2000-11-01), Lauterbach et al.
patent: 6154940 (2000-12-01), Onishi et al.
patent: 6197663 (2001-03-01), Chandross et al.
patent: 6236141 (2001-05-01), Sato et al.
patent: 6270202 (2001-08-01), Namba et al.
patent: 6448174 (2002-09-01), Ramm
patent: 6563224 (2003-05-01), Leedy
patent: 6593184 (2003-07-01), Han
Tong, Qin-Yi, et al, “Low Temperature Wafer Direct Bonding”, IEEE 1994, Journal of Microelectomechanical Systems, vol. 3, No. 1, Mar. 1994, pp. 29-35.
Gosele, U., et al, “Semiconductor Wafer Bonding, A Flexible Approach to Materials Combinations in Microelectronics, Micromechanics and Optoelectronics”, 1997 IEEE, pp. 23-32.
Takagi, Hideki, et al, “Low Temperature Direct Bonding of Silicon and Silicon Dioxide by the Surface Activation Method”, Transducers 1997, 1997 Int. Conf. on Solid State Sensors and Actuators Jun. 16-19, 1997, pp. 657-660.
Studies of SiO2-SiO2 Bonding with Hydrofluoric Acid—Room Temperature and Low Stress Bonding Technique for Mems, 1998 IEEE, pp. 609-614.
Fourson George
Ziptronix, Inc.
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