Three-dimensional high voltage transistor and method for...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257SE21410, C438S156000

Reexamination Certificate

active

11181561

ABSTRACT:
A method for manufacturing a three-dimensional high voltage transistor is disclosed. According to the method, lengths and widths of channels are increased while the reducing transistor forming area on plane, and semiconductor devices are completely separated from each other while restraining parasitic capacitance, latch-up phenomena, and formation of field transistors. The three-dimensional high voltage transistor includes an active area of the three-dimensional high voltage transistor formed in the form of a column on predetermined areas of a Silicon-On-Insulator substrate, source and drain formed in the active areas of the three-dimensional high voltage transistor in the depth direction, a channel area formed between the source and the drain in the depth direction, and a column-shaped gate formed at the side of the channel area on the Silicon-On-Insulator substrate.

REFERENCES:
patent: 6329240 (2001-12-01), Hsu et al.
patent: 6417540 (2002-07-01), Sugihara et al.
patent: 2006/0228840 (2006-10-01), Chau et al.
patent: 2007/0262384 (2007-11-01), Sato

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