Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2000-12-28
2002-09-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S459000, C438S465000
Reexamination Certificate
active
06448153
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to thinning and dicing of semiconductor wafers using a dry etch.
In many semiconductor fabrication processes, when circuitry has been fabricated in a semiconductor wafer, the wafer is thinned and then diced into chips. The thinning is typically performed with mechanical lapping. Dicing is performed with a diamond saw or a laser. The diamond saw or the laser can be used to cut the wafer all the way through along scribe lines. Alternatively, the wafer is cut part of the way through, and then broken.
The thinning and dicing processes can damage the wafer. It is desirable to provide alternative processes that reduce wafer damage and prolong the lifetime of hips obtained from the wafer.
SUMMARY
Some embodiments of the present invention reduce or eliminate wafer damage and prolong the chip lifetime by dicing the wafer part of the way through and then thinning the wafer with a dry etch. The chip lifetime is prolonged because the dry etch removes damage from chip surfaces and rounds the chip's edges and coners.
More particularly, as illustrated in
FIG. 1
, a chip
110
obtained by prior art thinning and dicing techniques may have uneven, damaged surfaces
110
B,
110
S, with sharp bottom coners and edges. Surface
110
B is the chip's backside, and surfaces
110
S are sidewalls. The wafer has been thinned from backside
110
B by mechanical lapping, and then diced along sidewalls
110
S with a diamond saw or a laser apparatus. These thinning and dicing processes damage the backside
110
B and sidewalls
110
S. The damage may include chipped, jagged surfaces, and microcracks. When the chip
110
is later packaged and put into use, the chip is subjected to heating and cooling cycles. These cycles cause the chip's packaging material (not shown) to exert stresses on the chip. Additional stresses can be developed inside the chip due to the thermal cycles, chip handling, or the presence of different materials or other non-uniformities inside the chip. Because the chip surfaces
110
B,
110
S are damaged, and because they intersect at sharp edges and coners, the stresses concentrate at isolated points on the chip surface. Further, microcracks weaken the chip's resistance to stress. As a result, the chip becomes less reliable. Cracks formed or extended by stresses in the chip can reach and damage the chip circuitry (not shown).
Dry etch provides smoother chip surfaces and rounded edges and corners. Damage is reduced or eliminated. The chip reliability is therefore improved.
In some embodiments of the present invention, the wafer is processed as follows. The wafer is diced to form grooves in the face side of the wafer. The grooves are at least as deep as the final thickness of each chip to be obtained from the wafer. Dicing can be performed with a diamond saw or a laser. The grooves' sidewalls can be damaged.
Then the wafer is placed into a non-contact wafer holder, and the wafer backside is etched with the dry etch until the grooves are exposed from the backside. The dry etch leaves the chips' backside smooth. In some embodiments, the dry etch continues after the grooves have been exposed from the backside. The etchant gets into the grooves and smoothens the chip sidewalls, removing at least some of the sidewall damage. The etchant also rounds the bottom coners and edges of the chips.
Suitable etches include atmospheric pressure plasma etches described, for example, in the aforementioned U.S. patent application Ser. No. 09/083,927. These etches are fairly fast. Silicon can be etched at 10 &mgr;m/min.
In some embodiments, the dry etch is a blanket uniform etch of the wafer's flat backside surface. No masking layers are used on the backside surface.
The invention is not limited to the embodiments described above. In some embodiments, one or more openings are formed in a first surface of a semiconductor wafer along a boundary of one or more chips. The openings do not go through the wafer. The wafer is placed into a non-contact wafer holder and thinned with a dry etch until the openings are exposed on a second side.
Other features of the invention are described below. The invention is defined by the appended claims.
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Halahan Patrick
Savastiouk Sergey
Siniaguine Oleg
Niebling John F.
Roman Angel
Shenker Michael
Skjerven Morrill LLP
Tru-Si Technologies Inc.
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