Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1999-04-07
2001-10-16
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S738000, C257S686000, C257S777000, C257S787000
Reexamination Certificate
active
06303997
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to semiconductor packages, and more particularly, to a semiconductor package that is responsive to the recent trend toward packages that are “super thin,” that have both improved electrical and heat dissipating performance, and that allow mounting of a plurality of stacked packages on a mother board to maximize the component density of the mother board.
2. Description of the Related Art
As is well appreciated by those skilled in the art, it is necessary to package memory devices or other semiconductor devices to enable them to be mounted on a mother board with a high package density. That is, in order to accomplish, e.g., a desired large memory capacity on a limited area of a mother board, the semiconductor packages must not only incorporate improved semiconductor chip integration techniques, but must also be designed to be mounted in relatively large numbers in a limited area on the mother board.
In an effort to increase the package density of a mother board, it has previously been proposed to mount a plurality of ball grid array (“BGA”) semiconductor packages on the mother board by stacking them, one on top of the other. In such an arrangement, the stacked packages form a single, interconnected, laminated package unit.
FIG. 1
shows such a stacked, laminated semiconductor package unit according to the prior art. As shown in the drawing, the laminated semiconductor package unit comprises a plurality of individual packages
100
′ stacked on top of each other.
Each of the above prior art packages
100
′ comprises a semiconductor chip
1
′ bonded to the top surface of a printed circuit board (“PCB”)
2
′ using a bonding agent
7
′. The input/output pads
1
a
′ of the chip
1
′ are electrically connected to a conductive circuit pattern
2
a
′ formed on the top surface of the PCB
2
′ by a wire bonding process using a plurality of conductive wires
3
′. The circuit pattern
2
a
′ is also electrically connected to a plurality of solder ball lands
2
b
′ formed on the lower surface of the PCB
2
′. The pattern
2
a
′ is electrically connected to the solder ball lands
2
b
′ by a plurality of conductive via holes (not shown). A solder ball
4
′ is welded to each of the solder ball lands
2
b
′. The top portion of the PCB
2
′ is encapsulated using a packaging material, such as an epoxy resin, thereby forming an encapsulated portion
5
′ that protects the chip
1
′ and the conductive wires
3
′ from the atmosphere.
In the above package
100
′, a portion of the circuit pattern
2
a
′ of the PCB
2
′ is exposed directly to the atmosphere, and a plurality of projection pads
8
′ are formed on the exposed portion in such a way such that the pads
8
′ project upwardly.
The packages
100
′ having the above-described construction may be individually mounted at distinct positions on a mother board. Alternatively, the packages
100
′ may be mounted on a mother board in a laminated, interconnected package unit wherein the individual packages
100
′ are stacked one on top of each other, as shown in FIG.
1
. Such a laminated package unit desirably increases the package density of the mother board.
In order to assemble and interconnect such a stacked, laminated package unit, the solder balls
4
′ that are formed on the lower surface of each upper package
100
′ are welded to the projection pads
8
′ that are formed on the top surface of each lower package
100
′.
However, the prior art laminated package unit is somewhat problematic in that the overall height of the unit typically exceeds a desirable maximum height, which is due to the cumulative thickness of each of the individual packages
100
′. That is, since the laminated package unit is formed by welding the solder balls
4
′ of each upper package
100
′ to the projection pads
8
′ of each lower package
100
′ as described above, the assembled unit resultingly has an excessive height, even though the unit may desirably increase the package density of a mother board. This excessive height of the laminated package unit effectively prevents an electronic device incorporating such a package from achieving a profile that is small, thin, and compact.
It may be noted that such a laminated package unit also necessarily increases the density of the heat emitted by the chips of the packages, but is lacking in any means for effectively dissipating that heat away from the chips and into the atmosphere. Therefore, packages incorporating the above prior art design typically exhibit significantly reduced processing speeds and mean-times-between-failure (“MTBFs”).
In addition, a conventional PCB for a semiconductor package typically has a relatively long circuit pattern on its top surface, thus lengthening the signal path and thereby adversely affecting the electrical performance of the package. Also, the individual packages of the typical stacked, laminated package unit typically incorporate a relatively expensive PCB, thereby increasing the production cost of the laminated package units.
SUMMARY OF THE INVENTION
The present invention has been made with the above problems of the prior art in mind, and accordingly, an object of the present invention is to provide a much thinner semiconductor package that is formed by using a lead frame having a plurality of projections on at least one of the upper and lower surfaces thereof, a package that also has both improved electrical and heat dissipating performance, and one that enables a plurality of such packages to be mounted on a mother board in a stacked, interconnected arrangement, thereby maximizing the package density of the mother board.
The above and other objects and advantages are achieved in a semiconductor package that, according to one embodiment of this invention, comprises a semiconductor chip having an integrated circuit. A plurality of input/output pads are disposed on a central portion of a first surface of the semiconductor chip for making electrical connections between the integrated circuit and an external circuit. A plurality of leads communicate with the exterior of the package. Each lead has an upper and a lower surface, one of which is bonded to the first surface of the semiconductor chip, and a projection having a raised surface formed on at least one of the upper and lower surfaces of the lead at a distal end thereof. The package also includes connection means for electrically connecting each lead of the plurality of leads to a corresponding input/output pad of the chip. An encapsulated portion envelops the semiconductor chip, plurality of leads and the connection means such that the raised surfaces of the projections are flush with an outer surface of the encapsulated portion. A plurality of solder balls are respectively welded to the raised surface of the projection of each lead of the plurality of leads to comprise signal input/output terminals of the package.
In the above embodiment, a second surface of the semiconductor chip opposite to the surface having the input/output pads on it is exposed to the atmosphere outside of the encapsulated portion, thus providing a means for effectively dissipating heat away from the chip during operation.
Another embodiment of this invention provides a semiconductor package, comprising a semiconductor chip having an integrated circuit with a plurality of input/output pads on a peripheral portion of a first surface of the chip for making electrical connections between the integrated circuit of the chip and an external circuit. A chip heat sink having a foot print that is smaller than the foot print of the chip is bonded to the first surface of the chip. A plurality of leads, each having an upper and a lower surface, one of which is bonded to the first surface of the semiconductor chip, communicates with the exterior of the semicon
Anam Semiconductor Inc.
Cruz Lourdes
Lee Eddie
LandOfFree
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