Thin polysilicon masking technique for improved lithography cont

Details Thin polysilicon masking technique for improved lithography cont Thin polysilicon masking technique for improved lithography cont

1997-03-21

1999-03-23

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438592, 438618, 438684, H01L 21336

Patent

active

058858792

ABSTRACT:
A process for fabricating a semiconductor transistor in which a semiconductor substrate is provided and a gate dielectric layer formed on an upper surface of the semiconductor substrate. A base conductive layer is then deposited on an upper surface of the gate dielectric layer. The base conductive layer is patterned to form base sections of a first and a second gate structure. Source/drain impurity distributions are introduced into the semiconductor substrate using the base sections as a mask to form source/drain structures within the semiconductor substrate. An insulating support layer is then formed on a topography defined by the semiconductor substrate and the base section. The insulating support layer is planarized until an upper surface of the insulating support layer is substantially planar with upper surfaces of the base sections. A second conductive layer is then deposited. The second conductive layer includes gate portions and interconnect portions. The gate portions reside above the base sections of the first and second gate structures. The interconnect portions reside above the insulating support layer. The second conductive layer is then patterned by removing selected areas of the interconnect portions of the second conductive layer. This process completes the first and second gate structures wherein each of the gate structures includes the base section and the gate portion of the second conductive layer. In this manner, a completed thickness of the first and second gate structures is greater than a thickness of the gate structures prior to the introduction of the source/drain impurity distributions.

REFERENCES:
patent: 4514233 (1985-04-01), Kawabuchi
patent: 4577392 (1986-03-01), Peterson
patent: 5102815 (1992-04-01), Sanchez
patent: 5352619 (1994-10-01), Hong
patent: 5376578 (1994-12-01), Hsu et al.
patent: 5674774 (1997-10-01), Pasch et al.

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