Thin floating gate and conductive select gate in situ doped...

Details Thin floating gate and conductive select gate in situ doped... Thin floating gate and conductive select gate in situ doped...

1999-07-13

2001-05-22

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S264000, C438S594000

Reexamination Certificate

active

06235586

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to improved methods of making flash memory devices such as EEPROMs. More particularly, the present invention relates to methods of making NAND type flash memory devices characterized by improved select gate performance.
BACKGROUND ART
Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art
FIG. 1
a
, a memory device such as a flash memory
10
comprises one or more high density core regions
11
and a low density peripheral portion
12
on a single substrate
13
. The high density core regions
11
typically consist of at least one M×N array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion
12
typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion
11
are coupled together in a NAND-type circuit configuration, such as, for example, the configuration illustrated in prior art
FIG. 1
b
. Each memory cell
14
has a drain
14
a
, a source
14
b
and a stacked gate
14
c
. A plurality of memory cells
14
connected together in series with a drain select transistor at one end and a source select transistor at the other end to form a NAND string as illustrated in prior art
FIG. 1
b
. Each stacked gate
14
c
is coupled to a word line (WL0, WL1, . . ., WLn) while each drain of the drain select transistors are coupled to a bit line (BL0, BL1, . . ., BLn). Lastly, each source of the source select transistors are coupled to a common source line Vss. Using peripheral decoder and control circuitry, each memory cell
14
can be addressed for programming, reading or erasing functions.
Prior art
FIG. 1
c
represents a fragmentary cross section diagram of a typical memory cell
14
in the core region
11
of prior art
FIGS. 1
a
and
1
b
. Such a cell
14
typically includes the source
14
b
, the drain
14
a
and a channel
15
in a substrate or P-well
16
; and the stacked gate structure
14
c
overlying the channel
15
. The stacked gate
14
c
further includes a thin gate dielectric layer
17
a (commonly referred to as the tunnel oxide) formed on the surface of the P-well
16
. The stacked gate
14
c
also includes a polysilicon floating gate
17
b
which overlies the tunnel oxide
17
a
and an interpoly dielectric layer
17
c
overlies the floating gate
17
b
. The interpoly dielectric layer
17
c
is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate
17
d
overlies the interpoly dielectric layer
17
c
. The control gates
17
d
of the respective cells
14
that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, for example, prior art
FIG. 1
b
). In addition, as highlighted above, the drain regions
14
a
of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel
15
of the cell
14
conducts current between the source
14
b
and the drain
14
a
in accordance with an electric field developed in the channel
15
by the stacked gate structure
14
c.
The process for making such NAND type flash memory devices includes numerous individual processing steps. There are numerous concerns associated with making flash memory devices that provide consistent performance and reliability. For example, the thicker the floating gate, the more likely undesirable cracking occurs in the tungsten silicide layer and the more likely etch problems occur due to high aspect ratios and high topographies. However, the thicker the floating gate, higher the stress released on the tunnel oxide layer, improved tunnel oxide reliability, improved conductivity and better circuit performance result. The thinner the floating gate, the more likely undesirable punch through during etch occurs, especially the Poly 1 contact etch for the select gate, as well as an undesirable increase in pinhole defects. Further, when the thickness of the Poly 1 is too thin, an HF dip cleaning step (prior to forming the ONO multilayer dielectric film) may degrade the Poly 1 and attack the tunnel oxide.
If the doping level is too low in the floating gate, wordline resistance and contact resistance become undesirably high, and specifically resistivity for the select gate becomes undesirably high. However, low doping results in a smooth tunnel oxide—floating gate interface. Low doping also results in fewer charge gain (loss) problems. If the doping level is too high in the floating gate, undesirable dopant segregation to the tunnel oxide occurs, undermining the tunnel oxide integrity. Undesirably high doping levels lead to severe surface roughness between the floating gate and the tunnel oxide, resulting in high local electric fields, lower oxide dielectric strength, and program/erase endurance cycling problems.
In view of the aforementioned concerns and problems, there is a need for flash memory cells of improved quality and more efficient methods of making such memory cells.
SUMMARY OF THE INVENTION
As a result of the present invention, non-volatile flash memory device fabrication is improved thereby producing devices having improved reliability. By employing the methods of the present invention which provide for specific parameters for making floating gates and select gates, the formation of a flash memory device having a low defect density, minimized charge gain/loss and low conductivity of select gate concerns from high/low Poly 1 doping, and fewer select gate interconnection problems is facilitated. Moreover, the methods of the present invention minimize and/or eliminate undesirable HF attack of tunnel oxide, high local electric fields, tungsten silicide cracking, and pinhole defects.
In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.
In another embodiment, the present invention relates to a method of forming a flash memory cell and a select gate transistor of a NAND type flash memory device, involving the steps of growing a first oxide layer having a thickness from about 130 Å to about 170 Å over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a p

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