Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-19
2003-02-11
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S059000, C257S072000
Reexamination Certificate
active
06518630
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a thin film transistor array substrate for a liquid crystal display and a method for fabricating the same.
(b) Description of the Related Art
Generally, liquid crystal displays have a structure where a liquid crystal is sandwiched between two substrates, and an electric field is applied to the liquid crystal to control light transmission. Electrodes are formed on the two substrates, and voltages are applied to the electrodes. One of the substrates has thin film transistors to switch the applied voltages, and is called a “thin film transistor array substrate.”
The thin film transistor array substrate is formed through photolithography using a number of masks. In order to reduce production cost, it is required that the number of masks be decreased.
Meanwhile, the signal lines for the thin film transistor array substrate are usually formed of a low resistance material such as aluminum (Al) or aluminum alloy (Al alloy) to prevent signal delay. However, indium tin oxide (ITO) commonly used for pad portions bears poor contact characteristic with the Al or Al alloy. Therefore, the Al or Al alloy at the pad portions should be replaced with another metallic material such as molybdenum (Mo) or chrome (Cr), and this results in complicated processing steps. In order to solve such a problem, it has been proposed that indium zinc oxide (IZO) should be used to form the pad portions while enhancing reliability thereof. However, in this case, the contact resistance at the pad portions increases while deteriorating the device performance characteristics.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a thin film transistor array substrate for a liquid crystal display which has low resistance material-based signal lines while insuring the reliability of pad portions.
It is another object of the present invention to provide a method for fabricating a thin film transistor array substrate in simplified processing steps.
These and other objects may be achieved by a thin film transistor array substrate having an intermetallic compound layer interposed between an aluminumbased layer and an indium zinc oxide layer.
The thin film transistor array substrate includes a substrate, and a gate wire formed on the substrate with a gate line and a gate electrode, a gate insulating layer covering the gate wire, and a semiconductor pattern formed on the gate insulating layer. A data wire is formed on the gate insulating layer and the semiconductor pattern with a data line, a source electrode and a drain electrode. The data wire bears a multiple-layered structure where a first metallic layer and an intermetallic compound layer are present. A protective layer is formed on the data wire and the semiconductor pattern. The drain electrode is exposed through a first contact hole, and a pixel electrode contacts the drain electrode. The intermetallic compound layer may be formed on the first metallic layer, and a second metallic layer may cover the intermetallic compound layer.
The first metallic layer may be formed with an aluminum-based metallic material, and the second metallic layer with molybdenum, titanium, tantalum or chrome. The intermetallic compound layer may be formed with a compound containing chrome, molybdenum, or molybdenum alloy.
The first contact hole may be formed in the protective layer, and the pixel electrode may contact the intermetallic compound layer for the drain electrode. Alternatively, the pixel electrode may contact the second metallic layer for the drain electrode.
According to one aspect of the present invention, in a method of fabricating the thin film transistor array substrate, a gate wire is formed on an insulating substrate through depositing a conductive layer on the substrate and patterning it. A gate insulating layer is then formed on the substrate such that the gate insulating layer covers the gate wire. A semiconductor layer is formed on the gate insulating layer. A conductive layer for data wire and a metallic layer are deposited on the gate insulating layer in a sequential manner, and performs an annealing process. The metallic layer is then removed, and the conductive layer for data wire is patterned to thereby form a data wire. A protective layer is deposited on the substrate such that the protective layer covers the data wire. A first contact hole is formed such that the drain electrode is exposed through the first contact hole, and a pixel electrode is formed such that the pixel electrode is electrically connected to the drain electrode. An intermetallic compound layer may be formed between the conductive layer for data wire and the metallic layer through the annealing.
According to another aspect of the present invention, in a method of fabricating the thin film transistor array substrate, a gate wire is formed on a substrate through depositing a conductive layer on the substrate and patterning it. A gate insulating layer is then formed on the substrate such that the gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A conductive layer for data wire and a metallic layer are deposited on the gate insulating layer and the semiconductor pattern in a sequential manner. The multiple-layered structure of the conductive layer for data wire and the metallic layer is then patterned to thereby form a data wire having a multiple-layered structure. A protective layer is formed such that the protective layer covers the semiconductor pattern. A first contact hole is formed such that the first contact hole exposes the drain electrode, and a pixel electrode is formed in the protective layer such that the pixel electrode is connected to the drain electrode through the first contact hole. An intermetallic compound may be formed between the conductive layer for data wire and the metallic layer through depositing the metallic layer at 150° C. or more.
REFERENCES:
patent: 5990986 (1999-11-01), Song et al.
patent: 6255706 (2001-07-01), Watanabe et al.
patent: 6376861 (2002-04-01), Yaegashi et al.
patent: 6377323 (2002-04-01), Ono et al.
Kong Hyang-Shik
You Chun-Gi
McGuireWoods LLP
Ngo Ngan V.
Park Hae-Chan
Samsung Electronics Co,. Ltd.
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