Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-09-23
2001-11-06
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S164000, C438S212000, C438S242000, C438S270000, C438S412000, C257S302000, C257S329000
Reexamination Certificate
active
06312992
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a thin film transistor and a method for fabricating the same, in which a channel width of the thin film transistor is made greater in a narrow area for improving an on/off performance of the thin film transistor.
2. Background of the Related Art
In general, the thin film transistor is used in place of a CMOS load transistor or a load resistor in an SRAM of 4M or 16M class or over, and also as a switching device for switching a video data signal from each pixel region in a liquid crystal display. Especially, as a PMOS thin film transistor(TFT) is used as a load transistor in the SRAM cell, an off-current in the load transistor can be reduced and an on-current in the load transistor can be increased, to reduce a power consumption in the SRAM cell and to improve a memory characteristic, allowing to obtain a high quality SRAM cell.
A background art thin film transistor and a method for fabricating the same will be explained with reference to the attached drawings.
FIG. 1
illustrates a section of the background art thin film transistor.
Referring to
FIG. 1
, the background art thin film transistor is provided with an insulating layer
21
, a gate electrode
22
a
on the insulating layer
21
, a gate insulating film
24
formed on the insulating layer
21
inclusive of the gate electrode
22
a
, a drain electrode D formed on the gate insulating film
24
spaced apart from the gate electrode
22
a
, a source electrode S formed on the gate insulating film
24
opposite to the drain electrode D overlapped with the gate electrode
22
a
, and a channel region I and an offset region II formed on the gate insulating film
24
between the source electrode S and the drain electrode D. The offset region II is a region between the drain electrode D and the gate electrode
22
a.
A background art method for fabricating a thin film transistor will be explained. FIGS.
2
A~
2
D illustrates sections showing the process steps of the background art method for fabricating a thin film transistor.
Referring to
FIG. 2A
, a first polysilicon layer
22
to be used as a gate electrode of a bulk transistor is formed on an insulating layer
21
. Photoresist is coated on the first polysilicon layer
22
and exposed and developed to form a mask pattern
23
. The first polysilicon layer
22
is selectively etched using the mask pattern
23
, to form a gate electrode
22
a
as shown in FIG.
2
B. Then, as shown in
FIG. 2C
, a gate insulating film
24
is deposited on the insulating layer
21
inclusive of the gate electrode
22
a
. A second polysilicon layer
25
to be used as source and drain electrodes, an offset region and a channel region is formed on the gate insulating film
24
. A photoresist
26
is coated on the second polysilicon layer
25
and patterned by exposure and development. As shown in
FIG. 2D
, the patterned photoresist
26
a
defines the channel region and the offset region. Then, impurity ions are injected into the exposed second polysilicon layer
25
using the patterned photoresist
26
a
as a mask, to form source/drain. Accordingly, the source electrode S is formed overlapped with a portion of the gate electrode
22
a
, and the drain electrode D is formed spaced from the gate electrode
22
a
. And, the channel region I and the offset region II are formed between the source electrode S and the drain electrode D.
However, the background art thin film transistor and the method for fabricating the same has a problem in that it has a lower on-current because the offset region is not influenced from a gate voltage.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a thin film transistor and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a thin film transistor and a method for fabricating the same which has an increased on-current and a wider channel in a small area.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the thin film transistor including a source electrode formed on a substrate, a columnar conductive layer connected to the source electrode, a drain electrode formed on the conductive layer, a gate insulating film formed to cover the conductive layer and the drain electrode, a gate electrode formed on the gate insulating film surrounding the conductive layer, and an insulting film formed between the source electrode and the gate electrode.
In other aspect of the present invention, there is provided a method for fabricating a thin film transistor, including the steps of (1) forming a source electrode on a substrate, (2) forming a columnar conductive layer connected to the source electrode, (3) forming an insulating film to a height on the substrate inclusive of the source electrode, (4) injecting ions to form a drain electrode in an upper part of the conductive layer, (5) forming a gate insulating film on the insulating film to cover the conductive layer and the drain electrode, and (6) forming a gate electrode on the gate insulating film covering the conductive layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5578838 (1996-11-01), Cho et al.
patent: 5612559 (1997-03-01), Park et al.
patent: 5659183 (1997-08-01), Manning et al.
patent: 5668391 (1997-09-01), Kim et al.
patent: 5728604 (1998-03-01), Rha et al.
patent: 5780888 (1998-07-01), Maeda et al.
patent: 5801397 (1998-09-01), Cunningham
patent: 5937283 (1999-08-01), Lee
patent: 5998839 (1999-12-01), Cho
patent: 6018176 (2000-01-01), Lim
patent: 6114725 (2000-09-01), Furukawa et al.
Diaz José R.
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Lee Eddie
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