Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-13
2001-10-09
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S049000, C257S050000, C257S051000, C257S059000, C257S064000, C257S065000
Reexamination Certificate
active
06300659
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a highly reliable thin-film transistor (TFT) and a fabrication method thereof. The thin-film transistor which is fabricated according to the present invention has the characteristic that it is formed on an insulating surface. In the present invention, an insulating surface does not only mean an insulating surface such as glass, but also includes an insulating covering which is provided on a semiconductor substrate such as amorphous silicon. In particular, the present invention relates to a thin-film transistor which has a process in which the source/drain regions are activated by thermal annealing.
2. Description of the Related Art
Research has been conducted recently on insulating gate-type semiconductor devices which have a thin-film semiconductor layer (also referred to as an active layer or active region) which is provided on an insulating surface. In particular, thin-film insulated gate transistors, so-called thin-film transistors (TFT) are earnestly studied. These are used in the drive circuits of matrix circuits, or for controlling pixels in an image device such as a liquid crystal display device which has a matrix construction formed on an insulating substrate, and they are also used in integrated circuits which have a three-dimensional construction, in which semiconductor integrated circuits are formed in multiple layers. TFTs are classified as amorphous silicon TFTs or crystalline silicon TFTs, depending on the material and crystalline form of the semiconductor being used.
In general the electric field mobility of semiconductors in the amorphous state is low, and they can therefore not be used in TFTs, which require high speed operation. Further, the P-type electric field mobility of amorphous silicon is very low, and therefore P-channel type TFTs (PMOS TFTs) cannot be fabricated, and it is consequently impossible to form complementary MOS circuits (CMOS) by combining with an N-channel type TFT (NMOS TFT).
However, the electric field mobility of crystalline semiconductors is higher than that of amorphous semiconductors, and therefore high speed operation is possible. Furthermore, with crystalline silicon, not only can NMOS TFTs be obtained, but also PMOS TFTs can be obtained in the same way, and therefore CMOS circuits can be formed; for example in an active matrix type liquid crystal display device, not only can the active matrix circuits, but also the peripheral circuits (driver circuit etc.) which drive this can be constructed on one and the same substrate using CMOS crystalline TFTs, and it is possible to obtain a so-called monolithic construction.
Recently, in order to reduce deterioration due to hot carriers, there has been a demand for the provision of low density impurity regions adjacent to the source or the drain regions, in which the density of N-type or P-type impurities is less than in the source/drain regions.
SUMMARY OF THE INVENTION
The problem in fabricating crystalline silicon TFTs is the process of activating the source/drain regions. The source/drain regions of a crystalline TFT and the low density impurity regions are normally formed by accelerating impurity ions which impart N-type or P-type conductor characteristics, and implanting them in a silicon film, as in the ion implantation method and the ion doping method, but at this time the silicon film is rendered amorphous by the ion impacts. Thus the sheet resistance of the source/drain regions in this amorphous state is extremely high.
With TFTs in which the semiconductor active layer is in the amorphous state, since the electric field mobility at first was small, such TFTs were useful provided that the sheet resistance of the source/drain regions was between approximately 10 k&OHgr;/□ and 1 M&OHgr;/□. However, since the electric field mobility with crystalline TFTs is high, it was not possible to obtain characteristics suitable for crystalline TFTs unless the sheet resistance was less than 10 k&OHgr;/□. It was thus necessary to increase the crystallinity of the amorphous source/drain regions (activation).
In the activation process, most of the portions of the TFT elements, beginning with the gate electrode, are, formed, and it is necessary to avoid damaging them. It is possible to use a thermal annealing process for the activation. This method has the feature that there is little variation between batches.
The temperature and time required for activation depends on the density of impurities. Thus whereas it is possible to perform activation at a relatively low temperature and for a short time by thermal annealing for the low density regions, regions in which impurities are implanted at high density, such as the source/drain regions require thermal annealing at high temperature for a long time. However, the gate electrode and substrate are liable to be greatly affected by thermal annealing at high temperature for a long time.
Normally, for a region in which impurities are implanted at a density of at least 1×10
20
atoms/cm
3
(at least 1×10
14
atoms/cm
3
when converted to a dosage), thermal annealing at a temperature of approximately 600° C. for a long time, or thermal annealing at a high temperature in excess of 1000° C. is required. If the latter method is adopted then selection of the substrate is limited to quartz, and the cost of the substrate becomes extremely high. On the other hand, although the former method has wide scope for selection of the substrate, the reduction in productivity due to thermal annealing for a long time is a major problem.
Further, in order to reduce the effects of heat on other portions of the element to a minimum (for example pattern slippage and the like due to shrinkage and distortion of the substrate) there has been a demand for activation by thermal annealing at lower temperatures and for a short time.
As a result of research by the present inventors it was discovered that by adding a trace amount of a catalyst material to a silicon covering in essentially an amorphous state it is possible to promote crystallization, lower the crystallization temperature and shorten the crystallization time. Suitable catalyst elements are nickel (Ni), iron (Fe), cobalt (Co), platinum (Pt) and palladium (Pd), either alone or in the form of compounds.
Specifically, methods for adding these catalyst elements to the silicon film include methods in which a film, particles or clusters, for example, containing the catalyst elements is formed such that it is essentially bonded below or above the amorphous silicon film, and methods in which the catalyst elements are introduced into the amorphous silicon film by a method such as ion implantation. After this it is possible to perform crystallization by thermal annealing the amorphous silicon film at a suitable temperature (typically a temperature of 580° C. or less).
Naturally, the relationship between temperature and time is such that as the annealing temperature increases, so the time required for crystallization decreases. Further, there is a relationship such that as the density of nickel, iron, cobalt or platinum, for example increases, so the temperature required for crystallization is reduced, and the time required for crystallization is reduced. Research by the present inventors showed that in order to promote crystallization, the density of at least one of these elements must exceed 1×10
17
/CM
3
in the amorphous silicon film which is to be crystallized.
However, since all of the abovementioned catalyst elements are materials which are not desirable in silicon, it is preferable for the densities thereof to be as low as possible. According to the research of the present inventors, it is desirable that the total density of the catalyst elements should not exceed 10
20
atoms/cm
3
.
The present inventors concentrated on the advantages of the catalyst elements, and by making use of them they discovered that it was possible to improve the crystallinity of the amorphous source/drain regions. To elaborate,
Takayama Toru
Takemura Yasuhiko
Zhang Hongyong
Abraham Fetsum
Nixon & Peabody LLP
Robinson Eric J.
Semiconductor Energy Laboratory Co,. Ltd.
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