Thin film forming method

Details Thin film forming method Thin film forming method

1997-04-11

2001-05-15

Meeks, Timothy (Department: 1762)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S695000, C438S763000, C427S569000, C427S579000, C427S255700, C156S228000, C156S247000, C156S308200

Reexamination Certificate

active

06232216

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a thin film forming method.
Multilevel interconnection technologies are essential to realize electronic components with a higher density. In mounting techniques, multilevel interconnections are realized by performing heating and pressing at high temperatures as described in ceramic substrate fabrication methods (Japanese Patent Laid-Open No. 4-356997). However, when multilevel interconnections are formed in LSIs, no high-temperature processing can be performed because devices are mounted.
To realize a multilevel interconnection structure in an LSI, therefore, it is necessary to completely planarize the surface of a dielectric film formed between interconnections.
Conventional representative technologies of this planarization process are SOG (Spin-On-Glass) and PIQ (K. Sato, S. Harada, A. Saiki, T. Kitamura, T. Okubo, and K. Mukai, “A Novel Planar Multilevel Interconnection Technology Utilization Polyimide”, IEEE Trans. Part Hybrid Package, PHP-9, 176 (1973)).
Other examples are etch back (P. Elikins, K. Reinhardt, and R. Layer, “A planarization process for double metal CMOS using Spin-on Glass as a sacrificial layer”, Proceeding of 3rd International IEEE VMIC Conf., 100 (1986)) and lift off (K. Ehara, T. Morimoto, S. Muramoto, and S. Matsuo, “Planar Interconnection Technology for LSI Fabrication Utilizing Lift-off Process”, J. Electrochem Soc., Vol. 131, No. 2, 419 (1984)).
On the other hand, bias-sputter was proposed as a simple planarization process (C. Y. Ting, V. J. Vivalda, and H. G. Schaefer, “Study of Planarized Sputter-Deposited-SiO
2
”, J. Vac. Sci. Technol. 15, 1105 (1978)).
Also, to be applied to finer interconnections, a planarization technology using bias ECR was proposed (K. Machida and H. Oikawa, “SiO
2
Planarization Technology with Biasing and Electron Cyclotron Resonance Plasma Deposition for Submicron Interconnections”, J. Vac. Sci. Technol. B4, 818 (1986)).
In these methods, while film formation is being performed by sputtering or ECR plasma CVD, an RF bias is applied to a substrate to cause sputtering on a substrate holder. These thin film forming methods perform film formation while etching convex regions by using the angle dependence of sputtering on a substrate, thereby accomplishing planarization. The characteristic features of these technologies are that thin film characteristics are good even when films are formed at low temperatures and the planarization processes are simple.
In the 1990's, chemical mechanical polishing was proposed as a method of planarizing the surface of an interlayer dielectric (W. J. Patrick, W. L. Guthrie, C. L. Standley, and P. M. Schiable,“Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circuit Interconnections”, J. Electrochem. Soc., Vol. 138, No. 6, June, 1778 (1991)). This chemical mechanical polishing attracted attention because a high degree of planarization could be obtained.
Recently, the diameter of substrates (wafers) on which semiconductor devices are formed have been increased steadily from 8 to 12 inches. When the above planarization technologies are applied to such large-diameter wafers, it is difficult for conventional thin film forming methods to secure the planarity and the uniformity of a film thickness over a broad range with a high controllability.
First, although SOG can easily form thin films, this method can be used only to, e.g., locally deposit a fine interconnection space or perform partial planarization.
Etch back is a technology being most extensively used but has the problem that dust is produced due to simultaneous etching of a resist and a dielectric film. Accordingly, etch back is not an easy technology in terms of control of dust and has a problem in the viewpoint of controllability.
On the other hand, lift off has the problem that a stencil used cannot be lifted off because this material does not completely dissolve during lift off. Due to the resulting insufficient controllability and yield, lift off has not been put into practical use.
Also, when the planarization technology using bias-sputter or bias ECR alone is used to perform planarization completely, the results are a low throughput (productivity) and damages to devices.
In chemical mechanical polishing, good chemical mechanical polishing characteristics cannot be obtained if the thin film characteristics of a dielectric film are unsatisfactory. Therefore, a high-quality dielectric film is necessary to be deposited at low temperatures. Additionally, this chemical mechanical polishing has a problem in controllability such as unstable chemical mechanical polishing characteristics.
SUMMARY OF THE INVENTION
It is, therefore, a principal object of the present invention to secure a high planarity and a high film thickness uniformity with a high controllability so as to cope with an increase of the diameter of wafers on which semiconductor devices are formed, and to form thin films at a low cost without producing dust.
To achieve the above object, there is provided a thin film forming method comprising the first step of forming a first thin film on a semiconductor substrate having a step height by chemical vapor deposition using a high density plasma, the second step of placing a base member on which a second thin film is formed on the semiconductor substrate such that the first and second thin films oppose each other, the third step of heating the semiconductor substrate to a first temperature to form the second thin film on the first thin film, and the fourth step of peeling off the base member from the second thin film.


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K. Sato, S. Harada, A. Saiki, T. Kitamura, T. Okubo, and K. Mukai, “A Novel Planar Multilevel Interconnection Technology Utilizing Polyimide”, IEEE Trans. Part Hybrid Package., PHP-9, 176(1973).
P. Elikins, K. Reinhardt, and R. Layer, “A planarization process for double metal CMOS using Spin-on Glass as a sacrificial layer, ” Proceeding of 3rd International IEEE VMIC Conf., 100 (1986).
K. Ehara, T. Morimoto, S. Muramoto, and S. Matsuo, “Planar Interconnection Technology for LSI Fabrication Utilizing Lift-off Process”, J. Electrochem. Soc., vol. 131, No. 2,419(1984).
C. Y. Ting, V. J. Vivalda, and H. G. Schaefer, “Study of Planarized Sputter-Deposited-SiO2”, J. Vac. Sci. Technol. 15, 1105(1978).
K. Machida and H. Oikawa, “SiO2Planarization Technology With Biasing and Electron Cyclotoron Resonance Plasma Deposition for Submicron Interconnections”, J. Vac. Sci. Technol. B4, 818(1986).
W. J. Patrick, W. L. Guthrie, C. L. Standley, P. M. Schiable, “Application of Chemical Mechanical Polishing to the Fabrication of VLSI Circutit Interconnections”, J. Electrochem. Soc., vol. 138, No. 6, Jun., 1778(1991).

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