Thicker oxide formation at the trench bottom by selective...

Details Thicker oxide formation at the trench bottom by selective... Thicker oxide formation at the trench bottom by selective...

2002-06-21

2004-03-23

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S212000, C438S268000, C438S272000, C438S589000

Reexamination Certificate

active

06709930

ABSTRACT:

BACKGROUND
Some metal-insulator-semiconductor (MIS) devices include a gate located in a trench that extends downward from the surface of a semiconductor substrate (e.g., silicon). The current flow in such devices is primarily vertical and, as a result, the cells can be more densely packed than devices with lateral current flow. All else being equal, this increases the current carrying capacity and reduces the on-resistance of the device. Devices included in the general category of MIS devices include metal-oxide-semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and MOS-gated thyristors.
Trench MOSFETs, for example, can be fabricated with a high transconductance (g
m,max
) and low specific on resistance (R
on
), which are important for optimal linear signal amplification and switching. One of the most important issues for high frequency operation, however, is reduction of the MOSFET internal capacitances. The internal capacitances include the gate-to-drain capacitance (C
gd
), which is also called the feedback capacitance (C
rss
), the input capacitance (C
iss
), and the output capacitance (C
oss
).
FIG. 1
is a cross-sectional view of a conventional n-type trench MOSFET
10
. In MOSFET
10
, an n-type epitaxial (“N-epi”) layer
13
, which is usually grown on an N
+
substrate (not shown), is the drain. N-epi layer
13
may be a lightly doped layer, that is, an N
−
layer. A p-type body region
12
separates N-epi layer
13
from N+ source regions
11
. Current flows vertically through a channel (denoted by the dashed lines) along the sidewall of a trench
19
. The sidewall and bottom of trench
19
are lined with a thin gate insulator
15
(e.g., silicon dioxide). Trench
19
is filled with a conductive material, such as doped polysilicon, which forms gate
14
. Trench
19
, including gate
14
therein, is covered with an insulating layer
16
, which may be borophosphosilicate glass (BPSG). Electrical contact to source regions
11
and body region
12
is made with a conductor
17
, which is typically a metal or metal alloy. Gate
14
is contacted in the third dimension, outside of the plane of FIG.
1
.
A significant disadvantage of MOSFET
10
is a large overlap region
18
formed between gate
14
and N-epi layer
13
, which subjects a portion of thin gate insulator
15
to the drain operating voltage. The large overlap limits the drain voltage rating of MOSFET
10
, presents long term reliability issues for thin gate insulator
15
, and greatly increases the gate-to-drain capacitance, C
gd
, of MOSFET
10
. In a trench structure, C
gd
is larger than in conventional lateral devices, limiting the switching speed of MOSFET
10
and thus its use in high frequency applications.
SUMMARY
In accordance with the present invention, a trench MOSFET is formed by creating a trench in a semiconductor substrate. A barrier layer is formed over a portion of the side wall of the trench. A thick insulating layer is then deposited in the bottom of the trench. The barrier layer is selected such that the thick insulating layer material deposits in the bottom of the trench at a faster rate than it deposits on the barrier layer. In some embodiments, the barrier layer is silicon nitride formed by chemical vapor deposition or silicon dioxide grown thermally. In some embodiments, the thick insulating layer is silicon dioxide.
Embodiments of the present invention offer several advantages. The thick insulating layer at the bottom of the trench improves device performance by reducing the gate-to-drain capacitance. Selective deposition of the thick insulating layer avoids stress and reliability problems often associated with thermal growth of thick oxide layers in the bottom of the trench. Also, selective deposition avoids the problems with control of the shape and thickness of the thick insulating layer encountered when a thick insulating layer is deposited, then etched to the proper shape and thickness.


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Pending U.S. application Ser. No. 10/180,154, filing date: Jun. 25, 2003.

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