Thermally enhanced semiconductor package

Details Thermally enhanced semiconductor package Thermally enhanced semiconductor package

2006-03-28

2006-03-28

Pham, Hoai (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S779000, C257S787000

Reexamination Certificate

active

07019406

ABSTRACT:
A thermally enhanced semiconductor package and a fabrication method thereof are provided. A plurality of conductive bumps are formed on bond pads on an active surface of a chip. A heat sink is attached to an inactive surface of the chip and has a surface area larger than that of the chip. An encapsulation body encapsulates the heat sink, chip and conductive bumps, while exposing a bottom or surfaces, not for attaching the chip, of the heat sink and ends of the conductive bumps outside. A plurality of conductive traces are formed on the encapsulation body and electrically connected to the ends of the conductive bumps. A solder mask layer is applied over the conductive traces and formed with a plurality of openings for exposing predetermined portions of the conductive traces. A solder ball is implanted on each exposed portion of the conductive traces.

REFERENCES:
patent: 5825087 (1998-10-01), Iruvanti et al.
patent: 6271469 (2001-08-01), Ma et al.
patent: 6287893 (2001-09-01), Elenius et al.
patent: 6507104 (2003-01-01), Ho et al.
patent: 6603198 (2003-08-01), Akram et al.
patent: 6661103 (2003-12-01), Akram

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