Thermal processing of semiconductor devices

Details Thermal processing of semiconductor devices Thermal processing of semiconductor devices

1998-09-01

2002-09-03

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S370000

Reexamination Certificate

active

06444549

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a fabrication process of semiconductor devices, and especially to a fabrication process of semiconductor devices suitable for use in bipolar transistors or biCMOS transistors.
2. Description of the Prior Art
With a view to reducing fabrication costs and shortening TAT (Turn Around Time; time from the acceptance of an order until its delivery), high-energy ion implantation (which means ion implantation with an acceleration voltage of several hundreds kev or higher) has been attempted as a substitute for the conventional epitaxial growth in recent years for the formation of buried collector layers for bipolar or biCMOS transistors.
Because of the need for a reduction in collector resistance to permit operation of a device at a higher speed, a dopant dose higher than that (<5×10
13
cm
−2
) employed to date for the formation of wells and the like is required upon high-energy ion implantation. However, use of a dose of about 1×10
14
cm
−2
or so is desired in view of the maintenance of an adequate balance between collector resistance and maximum collector-base breakdown voltage since a higher dose results in a lower maximum collector-base breakdown voltage.
All the same, formation of p+
junctions by ion implantation at an injection dopant dose around 1×10
14
cm
−2
and subsequent annealing by RTA (rapid thermal annealing) or an electric furnace under conditions of 10° C./sec or lower in terms of ramp-up rate is accompanied by a problem in that very large leakage currents occur across the junctions under the influence of defects extended to the surface of the sample from the neighborhood of the projection range of the ion implantation.
As a solution to this problem, Mat. Res. Soc. Symp. Proc. 396, 739 (1996, Materials Research Society) discloses that the leakage current across a junction can be reduced by RTA which makes use of a ramp-up rate of 50° C./sec or higher. It also discloses that, as the above-mentioned defects begin to grow abruptly when the temperature of RTA rises to 800° C., the leakage current can be reduced when the RTA is conducted by heating a wafer at a ramp-up rate of 50° C./sec or higher in the temperature range higher than or equal to 800° C. It is also disclosed that the leakage currents across the junctions of individual chips in a wafer can be lowered and their variations can be reduced to about half when RTA to a temperature of 1,050° C. is conducted by controlling the ramp-up rate at 1° C./sec from room temperature to 600° C. and at 100° C./sec beyond 600° C. instead of performing the heat treatment to the heat treatment temperature of 1,050° C. by using a ramp-up rate of 100° C./sec or higher from room temperature.
A ramp-up rate as low as 100° C./sec or so, however, involves a potential problem in that the above-described defects propagated from the projection range of ion implantation may grow to an area to which a depletion layer may extend upon application of a reverse bias. As soon as the depletion layer reaches a depth where defects exist, an increased leakage current occurs across the junction. According to the above-described conventional art, variations of leakage currents at a wafer surface may reach as much as 50% or so.
Namely, the process of the above-described conventional art is very effective in reducing the average value of leakage currents across junctions in a wafer, but further improvements are desired for the reduction of variations.
SUMMARY OF THE INVENTION
With the foregoing problems in view, the present invention has as a primary object thereof the provision of a process for the fabrication of semiconductors featuring both smaller leakage currents and reduced variations of the leakage currents even when ion implantation is conducted with high energy.
In a first aspect of the present invention, there is thus provided a fabrication process of semiconductor devices, which comprises the following steps:
subjecting a semiconductor substrate to ion implantation with high energy; and
heating the resulting ion-implanted semiconductor substrate to a temperature of from 1,000° C. to 1,200° C. at a ramp-up rate equal to or higher than 200° C./sec.
In this process, the temperature at which the heating is initiated at the ramp-up rate equal to or higher than 200° C./sec may preferably be from 600° C. to 800° C.
In a second aspect of the present invention, there is also provided a fabrication process of semiconductor devices, which comprises the following steps:
subjecting a semiconductor substrate to ion implantation with high energy;
heating the resulting ion-implanted semiconductor substrate to a temperature of from 1,000° C. to 1,200° C. at a ramp-up rate equal to or higher than 50° C./sec; and
subjecting the thus-heated semiconductor substrate to annealing at a temperature of from 1,000° C. to 1,200° C.
According to the first aspect of this invention, the heat treatment is conducted under hard conditions for the growth of defects occurred by the ion implantation so that, during the annealing step, the defects (dislocations) do not reach an area to which a depletion layer may extend. The process can therefore better reduce leakage currents and their variations than the conventional art. Further, the annealing at 1,200° C. and lower has made it possible to avoid the occurrence of slips (faults) in a wafer surface such as those occurring when the heat treatment is conducted at higher temperatures.
According to the second aspect of this invention, on the other hand, the ramp-up rate of 50° C./sec or higher is used, which includes ramp-up rates lower than those usable in the first aspect of the present invention. At such lower ramp-up rates, defects occurred as a result of the ion implantation may reach an area to which a depletion layer may extends. However, the subsequent heat treatment at a temperature of from 1,000° C. to 1,200° C. can eliminate the defects (dislocations) and restore the original crystalline structure, thereby making it possible to reduce leakage currents and their variations better than the conventional art.


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