Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-11-03
2001-09-18
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S266000, C257S669000, C257S698000
Reexamination Certificate
active
06291776
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a chip carrier, and more particularly, pertains to a chip carrier constituted of an organic laminate which incorporates structure compensating for thermal deformation of the carrier. Moreover, the invention relates to a method of counteracting the thermal deformations encountered by chip carriers, especially during solder reflow, which is predicated on the positioning of metal-plated through-holes (PTH) formed in the chip carrier.
In considering the structure of chip carriers, such as flip chip attach carriers, especially those which are constituted of organic laminates, the positioning of the plated through-holes (PTH) which provide for electrical interconnections between different printed circuit layers, the mismatch which is present in the thermal expansion (CTE) between the plated through-holes, in which the metal plating in the holes normally comprises copper, and the organic laminate material of the printed circuit board (PCB) or carrier, frequently results in both in-plane and out-of-plane thermal deformations of the carrier during solder reflow operations, which have an adverse effect on the reliability of the electrical connects at the locations of ball grid array (BGA) pads. In essence, the irregular or random spacings of the plated through-holes (PTH) with regard to the ball grid array (BGA) pads has evidenced that the closer the proximity of the plated through-hole to a BGA pad, this considerably increases the thermal deformation of the chip carrier at the location of the pad, adversely affecting product reliability through potential failures of the electrical connections at the pad position as a consequence of warpage of the organic material of the chip carrier.
Although publications presently address themselves to various problems associated with different types of arrangements of through-holes and vias extending through chip carriers, these generally do not concern themselves with compensating for thermal deformation stresses or strains tending to deform chip carrier, especially during solder reflow due to differentials or mismatches in the thermal expansion (CTE) which are present between the plated through-holes (PTH) and that of the organic laminate material of the chip carrier having the BGA pads thereon.
DISCUSSION OF THE PRIOR ART
Estes, et al., U.S. Pat. No. 5,451,720 which discloses a printed circuit board incorporating a thermal relief pattern in the form of a plurality of through-holes surrounding a via which is constructed to pass through a substrate consisting of an essentially organic laminate. Although the plurality of apertures define a thermal relief pattern, there is no disclosure of employing predetermined arrangements of plated through-holes for controlling deformations produced in the substrate by mismatches in the thermal expansion (CTE) between plated through-holes and organic laminate chip carrier which would have a tendency to adversely affect the integrity of electrical connections at ball grid array (BGA) pads located on the surface of the chip carrier.
Kondo, et al., U.S. Pat. No. 5,600,884 discloses a method of manufacturing electrical connecting members which incorporate recesses in spaced relationship with through-holes and electrically conductive elements extending therethrough. The recesses are positioned equidistantly intermediate the electrical connecting members and are arranged so as to reduce thermally generated stresses which could conceivably damage or sever the electrically conductive members. Chobot, et al., U.S. Pat. No. 5,473,813 discloses methods for the forming of electronic multi-layer printed circuit boards or cards and of an electronic packages incorporating the foregoing structures. Although the circuit boards incorporate through-holes in order to provide at least one thermal relief passage, there is no disclosure of correlating the positioning of plated through-holes (PTH) relative to ball grid array (BGA) pads on an organic laminate chip carrier so as to compensate for differentials in thermal expansion (CTE) pending to warp or deform the chip carrier and cause possible damage to the electrical interconnections and adversely affect their operative reliability.
McAllister, et al., U.S. Pat. No. 5,264,664 is directed to programmable chip to circuit board connections wherein apertures are provided so as to be able to accommodate connections forming a module.
Igarashi, U.S. Pat. No. 4,674,182 discloses the utilization of dummy patterns in order to prevent the warping of a printed circuit board component caused by uneven stresses which are generated through differences in thermal coefficients of expansion between the various employed materials.
Finally, Japanese Patent Publication No. 60-16701 discloses an electrically stable microwave printed circuit board having pin terminals shielded by providing through-hole structure adjacent thereto.
Although the foregoing publications are to varying degrees indirectly or directly concerned with stress relieving arrangements, and in some instances, those caused by mismatches in the thermal expansions (CTE) between electrical components or metallic components and organic laminate material chip carriers, none of these concern themselves with correlating the positioning of plated through-holes (PTH) relative to pads on an organic laminate chip carrier wherein the pads support ball grid arrays (BGA) so as to take into consideration thermal deformations of the organic laminate chip carrier during solder reflow processes, which are caused by mismatches in the coefficients or extent of thermal expansion (PTH) of the metallic-plated through-holes and the BGA pads positioned at predetermined spacings relative thereto.
SUMMARY OF THE INVENTION
Accordingly, in order to compensate for adverse thermal deformations of organic laminate chip carriers as presently encountered in the prior art, the invention is basically directed through the employment of novel arrangements and methods to solving the problems encountered in the effects of thermally-generated stresses and strains due to encountered by BGA pads the location relative thereto of plated through-holes (PTH) in chip carriers, wherein the carriers are generally of an organic laminate material and the ball grid array (BGA) pads are located in proximity to the plated through-holes. Basically, due to the presence of a mismatch in the coefficients or extent of thermal expansion (CTE) between the plated through-holes, the latter of which may be plated with copper or similar alloy materials, an investigation has evidenced thay by controlling the uniformity in the positioning or spacing of the plated through-holes (PTH) relative to the locations of the BGA pads on the organic laminate carrier, thermal deformations at the site of the pads can be controlled or eliminated so as to provide for a higher degree of reliability and long-term integrity of the electrical connections at those pad positions.
In order to accomplish the foregoing, pursuant to the present invention, a plurality of plated through-holes (PTH) are positioned equidistantly relative to contact (BGA) pads on a surface of a substrate which comprises an organic laminate material, so as to be able to control both in-plane and out-of-plane thermal deformations in the chip carrier material which may be occasioned in a solder reflow furnace or oven. The equidistant positioning of the plated through-holes relative to the BGA pads in comparison with the presently conventional random or irregularly spaced placement of the plated through-holes in the organic chip carrier has evidenced a significant improvement in the distribution and resultant reduction of stresses and strains generated caused by the differentials in the coefficients or extent of thermal expansion (CTE) between the plated through-holes and the organic chip carrier material supporting the BGA pads.
Accordingly, it is an object of the present invention to provide a chip carrier which comprises a substrate constituted of an organic material and which supports at lea
Markovich Voya R.
Moschak Peter A.
Park Seung-bae
Sathe Sanjeev B.
International Business Machines - Corporation
Kaschak Ronald A.
Paladini Albert W.
Scully Scott Murphy & Presser
LandOfFree
Thermal deformation management for chip carriers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thermal deformation management for chip carriers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thermal deformation management for chip carriers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2463153