Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-23
2002-05-14
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S294000, C438S311000, C438S430000
Reexamination Certificate
active
06387742
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to heat dissipation in semiconductor devices and, more particularly, to a structure and fabrication process which provides one or more thermally conducting studs in a semiconductor device to dissipate heat therefrom.
2. Background Description
Thermal conduction and heat dissipation is of great need in semiconductor devices due to the presence of the thermal heating from self heating of semiconductor components.
U.S. Pat. No. 5,714,791, issued to Chi et al. and entitled “On-chip Peltier Cooling Devices on a Micromachined Membrane Structure” discloses a Peltier cooling device generally useful in cooling electronic devices, especially those which are formed of high Tc superconducting materials. The Peltier device is formed on a micromachined membrane structure to assure good thermal isolation and to intimately integrate the cooling device with the electronic device it is to cool. The membrane is formed by selective, controlled etching of a bulk substrate of a material such as silicon. The Peltier device is formed by selectively implanting or depositing appropriate dopants to form n-doped and p-doped segments on the membrane with a junction between the differently doped segments at the approximate mid-point of the membrane.
U.S. Pat. No. 5,508,740, issued to Miyaguchi et al. and entitled “Solid-State Imaging Device Having Temperature Sensor” discloses a solid state image sensor that comprises a chip in a package. An image sensor is formed in the chip. The package has a main body, a light receiving glass plate fixed to the main body, and a buffer member arranged between the main body and light receiving glass plate. The buffer member is fixed to the light receiving glass plate and to the main body. The thermal expansion coefficient of the buffer member is substantially equal to that of the light receiving glass plate, so that the light receiving plate is fixed to the main body even though the temperature of the imaging device changes. Therefore, the adhesion is maintained between the main body and the light receiving glass plate and the airtightness in the package.
U.S. Pat. No. 5,403,783, issued to Nakanishi et al. and entitled “Integrated Circuit Substrate With Cooling Accelerator Substrate” discloses an electronic device that includes an integrated circuit device, comprising a first substrate including an integrated electronic semiconductor circuit and a second substrate including a cooling accelerator for accelerating a heat energy exchange between the integrated electronic semiconductor circuit and a cooling fluid.
U.S. Pat. No. 5,229,327, issued to Farnworth and entitled “Process for Manufacturing Semiconductor Device Structures Cooled by Peltier Junctions and Electrical Interconnect Assemblies Therefor” discloses a method for utilizing a single series operating current for providing operating power to an electronic device while simultaneously increasing or decreasing the cooling in a manner directly proportional to increases and decreases in power consumption and heat dissipation from the electronic device. The electronic device is connected to a first power supply terminal and a Peltier cooling junction is connected to one side of the electronic device. A Peltier heating junction is connected to one side of the Peltier cooling junction remote from the electronic device, and a heat sink is connected between the Peltier heating junction and a second power supply terminal. In this manner, a single series electrical circuit may be used for simultaneously providing operating power to the electronic device and cooling the electronic device in proportion to heat dissipation requirements therefor. Advantageously, the Peltier cooling and heating junctions may be formed in a planar fashion on the surface of a semiconductor die and used to cool integrated circuits which are fabricated within the die.
U.S. Pat. No. 5,040,381, issued to Hazen and entitled “Apparatus for Cooling Circuits” discloses an apparatus for cooling circuit modules by use of a thermo-electric device which comprises a series of semiconductor regions and etched copper conductors designed to conduct heat in a specified direction by means of the Peltier effect. The thermo-electric device is sandwiched between two layers of a polymer based, thermally conductive dielectric such as the dielectric used in the manufacture of Thermal Clad™. The hot layer of Thermal Clad™ (i.e., the layer that receives heat) is laminated directly to a heat sink. The cold layer of Thermal Clad™ is laminated directly to a cold plate which is, in turn, coupled to the circuit module.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a structure and fabrication process which provides for improved heat dissipation in semiconductor devices.
It is a further object of the invention to provide a structure and fabrication process which provides semiconductor elements with improved electrostatic discharge (ESD) robustness.
A first set of structures places a thermally conductive stud inside an isolation structure. It is preferred that the isolation structure is a single depth shallow trench isolation or a dual-depth trench isolation region. In general, the method of the present invention is suitable for trench isolation processes known in the art (e.g., dual depth).
An opening is formed in a shallow trench isolation (STI) region. An etch, preferably a reaction ion etch (RIE), forms a trough, which can extend either to a buried oxide (BOX) layer, or to the bulk silicon. The trough is optionally filled with a relatively thin layer of liner material, and then filled with a thermally conductive material, which is preferably polished so that it is substantially coplanar with a top surface of the structure. It is preferred that the thermally conductive material be one of heavily doped silicon, polysilicon, aluminum, copper, tungsten, refractory metals, or titanium, although other materials may also be used. Formation of the thermally conductive stud can be performed either early in the semiconductor process or in the Back End of Line (BEOL). It is preferred that the thermally conductive stud be placed within three thermal diffusion lengths of heat generating devices (HGDs) (e.g., metal oxide semiconductor field effect transistors (MOSFETs), bipolar devices, diodes, and, if desired, even interconnects).
A second set of structures comprises a first thermally conductive stud in the BOX layer, and a second thermally conductive stud in the isolation structure as described above with regard to the first embodiment. The first thermal stud may either be inactive or, in conjunction with the BOX layer and the HGD, form a buried gate structure of a dual gate SOI structure. The first thermal stud, in conjunction with the second thermal stud, allows both lateral and vertical thermal heat transport to the top surface and to the bulk substrate.
Both the first and second structures can either be capped or uncapped. The thermally conductive region (e.g., the area from which heat is conducted) can extend either to the buried oxide to the bulk substrate. It is also preferred in the second embodiment, as in the first embodiment, that the thermally conductive studs be positioned within three thermal diffusion lengths of any HGDs.
In contrast to the prior art references that utilize Peltier devices, the present invention provides a system and method that passively provides for heat dissipation in integrated circuit chips. In further contrast to the prior art references, the present invention integrates thermal heat transfer structures into a dual-gate silicon on insulator (SOI) technology, thereby providing a heat dissipation in dual-gate SOI technology.
REFERENCES:
patent: 4402185 (1983-09-01), Perchak
patent: 5040381 (1991-08-01), Hazen
patent: 5229327 (1993-07-01), Farnsworth
patent: 5403783 (1995-04-01), Nakanishi et al.
patent: 5508740 (1996-04-01), Miyaguchi et al.
patent: 5569621 (1996-10-01), Yallup et al.
patent: 5714791 (1998-02-01), Chi et
Gauthier Jr. Robert J.
Schepis Dominic J.
Tonti William R.
Voldman Steven H.
International Business Machines - Corporation
Jones Josetta I.
Niebling John F.
Shkurko Eugene I.
Whitham Curtis & Christofferson, P.C.
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