Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-03-13
2000-05-16
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714738, G01R 3128
Patent
active
06065144&
ABSTRACT:
A circuit for applying a testing data to a DUT for testing the DUT comprises a buffer memory for receiving and buffering a redundancy-free information as information which is substantially free of redundancy but might also comprise some redundant information to a certain extent, a redundancy memory for storing a redundancy information as information comprising a certain amount of redundancy, and a processing unit for generating the testing data by processing the redundancy-free information in association with the redundancy information. Further, includes a method for applying a testing data to the DUT for testing the DUT includes the steps of receiving and buffering the redundancy-free information, fetching in accordance with the received redundancy-free information the redundancy information, and generating the testing data by processing the redundancy-free information in association with the redundancy information.
REFERENCES:
patent: 4652814 (1987-03-01), Groves et al.
patent: 5157664 (1992-10-01), Waite
patent: 5317573 (1994-05-01), Bula et al.
patent: 5321701 (1994-06-01), Raymond et al.
Hewlett--Packard Company
Moise Emmanuel L.
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