Testing of circuit with plural clock domains

Details Testing of circuit with plural clock domains Testing of circuit with plural clock domains

2006-07-11

2006-07-11

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S731000

Reexamination Certificate

active

07076709

ABSTRACT:
An electronic circuit has a plurality of sub-circuits. Clock gate circuits supply gated clock signals to data storage elements of the sub-circuits. The clock gate circuits have gate inputs for receiving gate signals that commands blocking passage of the clock signal. Data can be transferred between data storage elements between two of the subcircuits. A detector circuit flags invalid data in the data storage element of the second one of the sub-circuits. The detector circuit has a flag storage element arranged to set a flag when the clock gate circuit of the second one of the sub-circuits passes the clock signal for the second one of the sub-circuits after the clock gate of the first one of the sub-circuits has blocked the clock signal for the first one of the sub-circuits. The flag indicates the relative phase of the clocks signals of different sub-circuits when the clocks are stopped. The flag is used to invalidate data in the data storage element of the second one of the sub-circuits.

REFERENCES:
patent: 5878055 (1999-03-01), Allen
patent: 6131173 (2000-10-01), Meirlevede et al.
patent: 6327684 (2001-12-01), Nadeau-Dostie et al.
patent: 6742151 (2004-05-01), Park et al.

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