Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-01-18
2003-01-07
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189070, C714S724000, C714S733000
Reexamination Certificate
active
06504772
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a testing method and test apparatus arranged in a semiconductor apparatus in which a to-be-tested circuit such as a random access memory (RAM) arranged in the semiconductor apparatus is tested to guarantee a correctly-performed normal operation of the semiconductor apparatus on condition that a redundancy circuit of the to-be-tested circuit is controlled according to a self-repair function of the semiconductor apparatus so as to avoid the use of a faulty portion of the to-be-tested circuit.
2. Description of Related Art
FIG. 17
is a block diagram showing the configuration of a conventional test device arranged in an electronic system (or a semiconductor apparatus) having a self-repair function. In the conventional test device arranged in the electronic system, a random access memory (RAM) of the electronic system is self-repaired by using the conventional test device.
In
FIG. 17
, a reference sign
100
indicates an electronic system (corresponding to a semiconductor apparatus) operable at each of a normal operation mode and a self-repair operation mode, and a reference sign
1
indicates a RAM to be self-tested and self-repaired. The RAM
1
has redundancy memory cells, so that a data storing capacity of the RAM
1
is larger than that required to perform a desired normal operation of the electronic system
100
. A reference sign
2
indicates a logical circuit. The RAM
1
and the logical circuit
2
are arranged to perform the desired normal operation of the electronic system
100
.
A reference sign
3
indicates a redundancy control circuit (hereinafter referred to as either redundancy control circuit or redundant control circuit). The redundancy control circuit
3
controls a signal transmission between the RAM
1
and the logical circuit
2
not to use a faulty portion of the RAM
1
at the normal operation mode of the electronic system
100
. Also, the redundancy control circuit
3
controls a signal transmission between the RAM
1
and a RAM built-in self test circuit described later at the self-repair operation mode of the electronic system
100
.
A reference sign
4
indicates the RAM built-in self-test circuit described above, and the RAM built-in self-test circuit
4
generates a test pattern to test the RAM
1
in the self-repair operation, checks output data produced in the RAM
1
in response to the test pattern and outputs a test result indicating whether the RAM
1
is correctly operated. A reference sign
5
indicates a RAM built-in self-repair circuit arranged for the RAM
1
. The RAM built-in self-repair circuit
5
controls the redundant control circuit
3
at each of the operation modes (the normal operation mode and the self-repair operation mode), controls the RAM built-in self-test circuit
4
at the self-repair operation mode, collects the test result from the RAM built-in self-test circuit
4
at the self-repair operation mode and judges according to the test result whether or not the repair of the RAM
1
is possible.
A reference sign
6
indicates a logic built-in self-test circuit arranged to test the logical circuit
2
. The logic built-in self-test circuit
6
generates pseudo-random numbers to test the logical circuit
2
and compresses an output result produced in the logical circuit
2
in response to the pseudo-random numbers.
The test device arranged in the electronic system
100
(or the semiconductor apparatus) is composed of the logical circuit
2
, the RAM built-in self-test circuit
4
, the RAM built-in self-repair circuit
5
and the logic built-in self-test circuit
6
.
To compress the test result in the RAM built-in self-test circuit
4
, a signature register type compressing unit is generally used. Also, because the logic built-in self-test circuit
6
is not necessarily required to perform a self-repair operation for the RAM
1
, there is a case that the logic built-in self-test circuit
6
is omitted.
Next, an operation of the conventional test device is described.
FIG. 18
is a flow chart showing the procedure of a self-repair operation performed by the conventional test device shown in FIG.
17
.
In a self-repair operation, the RAM built-in self-repair circuit
5
controls the redundant control circuit
3
and the RAM built-in self-test circuit
4
, a test pattern generated in the RAM built-in self-test circuit
4
is transmitted to the RAM
1
, and a test of the RAM
1
is performed (step ST
1
). In detail, output data of the RAM
1
is obtained in the RAM built-in self-test circuit
4
through the redundant control circuit
3
, and it is judged by the RAM built-in self-test circuit
4
according to the output data whether or not a faulty portion exists in the RAM
1
.
In cases where a faulty portion exists in the RAM
1
, the RAM built-in self-repair circuit
5
collects a test result from the RAM built-in self-test circuit
4
, and it is judged by the RAM built-in self-repair circuit
5
according to the test result whether or not the repair of the faulty portion of the RAM
1
is possible (step ST
2
). In cases where the repair of the faulty portion of the RAM
1
is possible, the RAM built-in self-repair circuit
5
controls the redundant control circuit
3
not to use the faulty portion of the RAM
1
in a normal operation(step ST
3
). That is, the redundant control circuit
3
controls the RAM
1
to use its redundancy memory cells in place of the faulty portion in the normal operation.
The above-described test device arranged in the electronic system
100
(or the semiconductor apparatus) having a self-repair function is, for example, disclosed in the Published Unexamined Japanese Patent Application H8-94718 (1996). Also, as is described in the U.S. Pat. No. 5,956,350, a technique, in which a self-repair is performed to avoid the use of faulty locations under a system temperature-rise condition, is known.
However, because the RAM built-in self-repair circuit
5
controls the redundant control circuit
3
according to a result of one test performed for the RAM
1
in the conventional test device, in cases where a fault not detected under ordinary conditions (for example, ordinary power supply voltage and temperature) set in one test exists in the RAM
1
, there is a problem that a control of the RAM built-in self-repair circuit
5
for the redundant control circuit
3
to avoid the use of a portion relating to the faulty of the RAM
1
in specific conditions differing from the ordinary conditions cannot be correctly performed.
For example, in cases where a self-test of the electronic system
100
for the RAM
1
is performed just after an electric power is supplied to the electronic system
100
set to a low temperature (or an ambient temperature), a specific fault of the RAM
1
occurring only in cases where the RAM
1
is heated up to a high temperature corresponding to a stationary temperature in a normal operation of the electronic system
100
cannot be detected. In cases where the specific fault exists in the RAM
1
, the electronic system
100
malfunctions under the high temperature condition.
In contrast, as is described in the U.S. Pat. No. 5,956,350, in cases where a self-test of the electronic system
100
for the RAM
1
is performed under a high temperature condition, a fault of the RAM
1
occurring only in cases where the RAM
1
is set to a low temperature cannot be detected. In cases where this fault exists in the RAM
1
, the electronic system
100
malfunctions under the low temperature condition. Because the electronic system
100
has a power save function, there is a case that the electronic system
100
is cooled to a low temperature even though the electric power is supplied to the electronic system
100
. Also, in cases where the electronic system
100
is a portable device, the electronic system
100
is cooled to a low temperature when an ambient temperature is suddenly lowered. Therefore, there is a problem in cases where a self-test of the electronic system
100
for the RAM
1
is performed under a hig
Burns Doane , Swecker, Mathis LLP
Dinh Son T.
Mitsubishi Denki & Kabushiki Kaisha
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