Testing IO timing in a delay locked system using separate...

Details Testing IO timing in a delay locked system using separate... Testing IO timing in a delay locked system using separate...

1999-06-08

2002-07-16

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S814000

Reexamination Certificate

active

06421801

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of integrated circuits and, more specifically, to the testing of high speed input, paths in integrated circuits.
BACKGROUND
Test systems are used to evaluate integrated circuits to determine whether the integrated circuits meet manufacturing and design specifications. An integrated circuit is tested by connecting a test system to pads located on the integrated circuit. The integrated circuit is subjected to functional and parametric testing. Some of the testing may include the measurement of key input/output (I/O) timing parameters, such as input data setup and hold times. The tester transmits signals to stimulate the integrated circuit and then measures responses from the integrated circuit. The signals are generated by the tester using edge generators. An edge generator contains driver circuitry to produce a signal having an edge at a certain time relative to start of a timing period. A high resolution edge placement accuracy is required when testing high speed I/O paths. As such, resolution inaccuracies in the tester may effect the measurement of critical I/O timing parameters.
One prior art testing method uses an output buffer and delay element to perform relative I/O timing measurements. One problem with such a testing method is that it is susceptible to signal coupling from adjacent bondpad wires and loading from external elements, resulting in the generation of noise in a tested parameter. Such noise results in measurement inaccuracies that may cause the testing method to be unreliable.
SUMMARY OF THE INVENTION
A method and apparatus for testing an input data path of an integrated circuit is described. The method includes setting a first timing parameter of a first clock signal to match a second timing parameter of a second clock signal, the first timing parameter having a first value. The method also including applying a data pattern to the input data path to produce an output based on the first and second timing parameters, and comparing the data pattern with the output of the input data path.
Additional features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.


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